src/mainboard/google/hatch/variants/kohaku/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <baseboard/gpio.h>
   5 #include <baseboard/variants.h>
   6 #include <commonlib/helpers.h>
   7
   8 static const struct pad_config gpio_table[] = {
   9         /* A8  : PEN_GARAGE_DET_L (wake) */
  10         PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE),
  11         /* A12 : FPMCU_RST_ODL */
  12         PAD_CFG_GPO(GPP_A12, 0, DEEP),
  13         /* A16 : EMR_GARAGE_DET (notification) */
  14         PAD_CFG_GPI_GPIO_DRIVER(GPP_A16, NONE, PLTRST),
  15         /* A17 : PIRQA# ==> NC */
  16         PAD_NC(GPP_A17, NONE),
  17         /* A18 : ISH_GP0 ==> NC */
  18         PAD_NC(GPP_A18, NONE),
  19         /* A19 : PEN_RESET_ODL */
  20         PAD_CFG_GPO(GPP_A19, 0, DEEP),
  21         /* A20 : ISH_GP2 ==> NC */
  22         PAD_NC(GPP_A20, NONE),
  23         /* A22 : ISH_GP4 ==> NC */
  24         PAD_NC(GPP_A22, NONE),
  25         /* B8  : SRCCLKREQ3#: NC  */
  26         PAD_NC(GPP_B8, NONE),
  27         /* C1  : SMBDATA: NC  */
  28         PAD_NC(GPP_C1, NONE),
  29         /* C7  : PEN_IRQ_OD_L */
  30         PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT),
  31         /* C12 : EN_PP3300_TSP_DX */
  32         PAD_CFG_GPO(GPP_C12, 1, DEEP),
  33         /* C13 : EC_PCH_INT_L - needs to wake the system */
  34         PAD_CFG_GPI_IRQ_WAKE(GPP_C13, NONE, PLTRST, LEVEL, INVERT),
  35         /* C15 : EN_PP3300_DIG_DX */
  36         PAD_CFG_GPO(GPP_C15, 0, DEEP),
  37         /* C23 : UART2_CTS# ==> NC */
  38         PAD_NC(GPP_C23, NONE),
  39         /* D15 : TOUCHSCREEN_RST_L */
  40         PAD_CFG_GPO(GPP_D15, 1, DEEP),
  41         /* D16 : TOUCHSCREEN_INT_L */
  42         PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT),
  43         /* E23 : GPP_E23 ==> NC */
  44         PAD_NC(GPP_E23, NONE),
  45         /* F1 : GPP_F1 ==> NC */
  46         PAD_NC(GPP_F1, NONE),
  47         /* F11 : PCH_MEM_STRAP_2 */
  48         PAD_CFG_GPI(GPP_F11, NONE, PLTRST),
  49         /* F20 : PCH_MEM_STRAP_0 */
  50         PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
  51         /* F21 : PCH_MEM_STRAP_1 */
  52         PAD_CFG_GPI(GPP_F21, NONE, PLTRST),
  53         /* F22 : PCH_MEM_STRAP_3 */
  54         PAD_CFG_GPI(GPP_F22, NONE, PLTRST),
  55         /* G0 : GPP_G0 ==> NC  */
  56         PAD_NC(GPP_G0, NONE),
  57         /* G1 : GPP_G1 ==> NC  */
  58         PAD_NC(GPP_G1, NONE),
  59         /* G2 : GPP_G2 ==> NC  */
  60         PAD_NC(GPP_G2, NONE),
  61         /* G3 : GPP_G3 ==> NC  */
  62         PAD_NC(GPP_G3, NONE),
  63         /* G4 : GPP_G4 ==> NC  */
  64         PAD_NC(GPP_G4, NONE),
  65         /* G5 : GPP_G5 ==> NC  */
  66         PAD_NC(GPP_G5, NONE),
  67         /* G6 : GPP_G6 ==> NC  */
  68         PAD_NC(GPP_G6, NONE),
  69         /* H3  : SPKR_PA_EN */
  70         PAD_CFG_GPO(GPP_H3, 0, DEEP),
  71         /* H4  : PCH_I2C_PEN_SDA */
  72         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
  73         /* H5  : PCH_I2C_PEN_SCL */
  74         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
  75 };
  76
  77 const struct pad_config *override_gpio_table(size_t *num)
  78 {
  79         *num = ARRAY_SIZE(gpio_table);
  80         return gpio_table;
  81 }
  82
  83 /*
  84  * GPIOs configured before ramstage
  85  * Note: the Hatch platform's romstage will configure
  86  * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins
  87  * as inputs before it reads them, so they are not
  88  * needed in this table.
  89  */
  90 static const struct pad_config early_gpio_table[] = {
  91         /* B15 : H1_SLAVE_SPI_CS_L */
  92         PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
  93         /* B16 : H1_SLAVE_SPI_CLK */
  94         PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
  95         /* B17 : H1_SLAVE_SPI_MISO_R */
  96         PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
  97         /* B18 : H1_SLAVE_SPI_MOSI_R */
  98         PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
  99         /* C8  : UART_PCH_RX_DEBUG_TX */
 100         PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
 101         /* C9  : UART_PCH_TX_DEBUG_RX */
 102         PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 103         /* C14 : BT_DISABLE_L */
 104         PAD_CFG_GPO(GPP_C14, 0, DEEP),
 105         /* PCH_WP_OD */
 106         PAD_CFG_GPI(GPP_C20, NONE, DEEP),
 107         /* C21 : H1_PCH_INT_ODL */
 108         PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
 109         /* C22 : EC_IN_RW_OD */
 110         PAD_CFG_GPI(GPP_C22, NONE, DEEP),
 111         /* E1  : M2_SSD_PEDET */
 112         PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
 113         /* E5  : SATA_DEVSLP1 */
 114         PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
 115         /* F2  : MEM_CH_SEL */
 116         PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
 117         /* F11 : PCH_MEM_STRAP2 */
 118         PAD_CFG_GPI(GPP_F11, NONE, PLTRST),
 119         /* F20 : PCH_MEM_STRAP0 */
 120         PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
 121         /* F21 : PCH_MEM_STRAP1 */
 122         PAD_CFG_GPI(GPP_F21, NONE, PLTRST),
 123         /* F22 : PCH_MEM_STRAP3 */
 124         PAD_CFG_GPI(GPP_F22, NONE, PLTRST),
 125 };
 126
 127 const struct pad_config *variant_early_gpio_table(size_t *num)
 128 {
 129         *num = ARRAY_SIZE(early_gpio_table);
 130         return early_gpio_table;
 131 }
 132
 133 /* Set the FPMCU SPI CS line very late to workaround
 134  * leakage of this line onto the VDD of the MCU.
 135  */
 136 static const struct pad_config finalize_gpio_table[] = {
 137         /* A11 : PCH_SPI_FPMCU_CS_L */
 138         PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2),
 139 };
 140
 141 /*
 142  * GPIOs configured during the mainboard finalize
 143  */
 144 const struct pad_config *variant_finalize_gpio_table(size_t *num)
 145 {
 146         *num = ARRAY_SIZE(finalize_gpio_table);
 147         return finalize_gpio_table;
 148 }
 149
 150 /*
 151  * Default GPIO settings before entering non-S5 sleep states.
 152  * Configure A12: FPMCU_RST_ODL as GPO before entering sleep.
 153  * This guarantees that A12's native3 function is disabled.
 154  * See https://review.coreboot.org/c/coreboot/+/32111 .
 155  */
 156 static const struct pad_config default_sleep_gpio_table[] = {
 157         PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
 158 };
 159
 160 /*
 161  * GPIO settings before entering S5, which are same as
 162  * default_sleep_gpio_table but also, turn off FPMCU.
 163  */
 164 static const struct pad_config s5_sleep_gpio_table[] = {
 165         PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */
 166         PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */
 167 };
 168
 169 const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num)
 170 {
 171         if (slp_typ == ACPI_S5) {
 172                 *num = ARRAY_SIZE(s5_sleep_gpio_table);
 173                 return s5_sleep_gpio_table;
 174         }
 175         *num = ARRAY_SIZE(default_sleep_gpio_table);
 176         return default_sleep_gpio_table;
 177 }
 178
 179 /* GPIOs needed to be set in romstage. */
 180 static const struct pad_config romstage_gpio_table[] = {
 181         /* Enable touchscreen, hold in reset */
 182         /* C12 : EN_PP3300_TSP_DX */
 183         PAD_CFG_GPO(GPP_C12, 1, DEEP),
 184         /* D15 : TOUCHSCREEN_RST_L */
 185         PAD_CFG_GPO(GPP_D15, 0, DEEP),
 186 };
 187
 188 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 189 {
 190         *num = ARRAY_SIZE(romstage_gpio_table);
 191         return romstage_gpio_table;
 192 }