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mb/google/fatcat/var/fatcat: Refactor GPIO programming for UFS support
[coreboot.git] / src / mainboard / google / myst / variants / baseboard / devicetree.cb
blob62e19bf75a6ffe28da71ebc947459f99cf763c88
1 # SPDX-License-Identifier: GPL-2.0-or-later
2 chip soc/amd/phoenix
3
4 # eSPI Configuration
5 # TODO(b/276913952) bump clock back up to 33MHz once things seem to be working well.
6 register "common_config.espi_config" = "{
7 .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN,
8 .generic_io_range[0] = {
9 .base = 0x62,
10 .size = 1,
11 },
12 .generic_io_range[1] = {
13 .base = 0x66,
14 .size = 1,
15 },
16 .generic_io_range[2] = {
17 .base = 0x800, /* EC_HOST_CMD_REGION0 */
18 .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */
19 },
20 .generic_io_range[3] = {
21 .base = 0x900, /* EC_LPC_ADDR_MEMMAP */
22 .size = 255, /* EC_MEMMAP_SIZE */
23 },
24 .generic_io_range[4] = {
25 .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */
26 .size = 8, /* 0x200 - 0x207 */
27 },
28
29 .io_mode = ESPI_IO_MODE_QUAD,
30 .op_freq_mhz = ESPI_OP_FREQ_16_MHZ,
31 .crc_check_enable = 1,
32 .alert_pin = ESPI_ALERT_PIN_OPEN_DRAIN,
33 .periph_ch_en = 1,
34 .vw_ch_en = 1,
35 .oob_ch_en = 0,
36 .flash_ch_en = 0,
37
38 .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1),
39 }"
40
41 register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
42 GPIO_I2C2_SCL | GPIO_I2C3_SCL"
43
44 # I2C Pad Control RX Select Configuration
45 register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" # Trackpad
46 register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" # Touchscreen
47 register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # GSC
48 register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # Speaker, Codec, P-SAR, USB
49
50 # I2C Config
51 #+-------------------+----------------------------+
52 #| Field | Value |
53 #+-------------------+----------------------------+
54 #| I2C0 | Trackpad |
55 #| I2C1 | Touchscreen |
56 #| I2C2 | GSC TPM |
57 #| I2C3 | Speaker, Codec, P-SAR, USB |
58 #+-------------------+----------------------------+
59 register "i2c[0]" = "{
60 .speed = I2C_SPEED_FAST,
61 }"
62
63 register "i2c[1]" = "{
64 .speed = I2C_SPEED_FAST,
65 }"
66
67 register "i2c[2]" = "{
68 .speed = I2C_SPEED_FAST,
69 .early_init = true,
70 }"
71
72 register "i2c[3]" = "{
73 .speed = I2C_SPEED_FAST,
74 }"
75
76 # general purpose PCIe clock output configuration
77 register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN
78 register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD
79 register "gpp_clk_config[2]" = "GPP_CLK_REQ" # WWAN
80 register "gpp_clk_config[3]" = "GPP_CLK_REQ" # SSD
81 register "gpp_clk_config[4]" = "GPP_CLK_OFF" # SOC_FP_BOOT0 GPIO
82 register "gpp_clk_config[5]" = "GPP_CLK_OFF" # WLAN_AUX_RST_L GPIO
83 register "gpp_clk_config[6]" = "GPP_CLK_OFF" # WWAN_AUX_RST_L GPIO
84
85 register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO(b/277214353): reenable when PSPP works
86 register "s0ix_enable" = "true"
87
88 register "usb_phy_custom" = "1"
89 register "usb_phy" = "{
90 .Usb2PhyPort[0] = {
91 .compdistune = 0x3,
92 .pllbtune = 0x1,
93 .pllitune = 0x0,
94 .pllptune = 0xe,
95 .sqrxtune = 0x3,
96 .txfslstune = 0x3,
97 .txpreempamptune = 0x2,
98 .txpreemppulsetune = 0x0,
99 .txrisetune = 0x1,
100 .txvreftune = 0x3,
101 .txhsxvtune = 0x3,
102 .txrestune = 0x2,
103 },
104 .Usb2PhyPort[1] = {
105 .compdistune = 0x3,
106 .pllbtune = 0x1,
107 .pllitune = 0x0,
108 .pllptune = 0xe,
109 .sqrxtune = 0x3,
110 .txfslstune = 0x3,
111 .txpreempamptune = 0x2,
112 .txpreemppulsetune = 0x0,
113 .txrisetune = 0x1,
114 .txvreftune = 0x3,
115 .txhsxvtune = 0x3,
116 .txrestune = 0x2,
117 },
118 .Usb2PhyPort[2] = {
119 .compdistune = 0x3,
120 .pllbtune = 0x1,
121 .pllitune = 0x0,
122 .pllptune = 0xe,
123 .sqrxtune = 0x3,
124 .txfslstune = 0x3,
125 .txpreempamptune = 0x2,
126 .txpreemppulsetune = 0x0,
127 .txrisetune = 0x1,
128 .txvreftune = 0x3,
129 .txhsxvtune = 0x3,
130 .txrestune = 0x2,
131 },
132 .Usb2PhyPort[3] = {
133 .compdistune = 0x3,
134 .pllbtune = 0x1,
135 .pllitune = 0x0,
136 .pllptune = 0xe,
137 .sqrxtune = 0x3,
138 .txfslstune = 0x3,
139 .txpreempamptune = 0x2,
140 .txpreemppulsetune = 0x0,
141 .txrisetune = 0x1,
142 .txvreftune = 0x3,
143 .txhsxvtune = 0x3,
144 .txrestune = 0x2,
145 },
146 .Usb2PhyPort[4] = {
147 .compdistune = 0x3,
148 .pllbtune = 0x1,
149 .pllitune = 0x0,
150 .pllptune = 0xe,
151 .sqrxtune = 0x3,
152 .txfslstune = 0x3,
153 .txpreempamptune = 0x2,
154 .txpreemppulsetune = 0x0,
155 .txrisetune = 0x1,
156 .txvreftune = 0x3,
157 .txhsxvtune = 0x3,
158 .txrestune = 0x2,
159 },
160 .Usb2PhyPort[5] = {
161 .compdistune = 0x3,
162 .pllbtune = 0x1,
163 .pllitune = 0x0,
164 .pllptune = 0xe,
165 .sqrxtune = 0x3,
166 .txfslstune = 0x3,
167 .txpreempamptune = 0x2,
168 .txpreemppulsetune = 0x0,
169 .txrisetune = 0x1,
170 .txvreftune = 0x3,
171 .txhsxvtune = 0x3,
172 .txrestune = 0x2,
173 },
174 .Usb2PhyPort[6] = {
175 .compdistune = 0x3,
176 .pllbtune = 0x1,
177 .pllitune = 0x0,
178 .pllptune = 0xe,
179 .sqrxtune = 0x3,
180 .txfslstune = 0x3,
181 .txpreempamptune = 0x2,
182 .txpreemppulsetune = 0x0,
183 .txrisetune = 0x1,
184 .txvreftune = 0x3,
185 .txhsxvtune = 0x3,
186 .txrestune = 0x2,
187 },
188 .Usb2PhyPort[7] = {
189 .compdistune = 0x3,
190 .pllbtune = 0x1,
191 .pllitune = 0x0,
192 .pllptune = 0xe,
193 .sqrxtune = 0x3,
194 .txfslstune = 0x3,
195 .txpreempamptune = 0x2,
196 .txpreemppulsetune = 0x0,
197 .txrisetune = 0x1,
198 .txvreftune = 0x3,
199 .txhsxvtune = 0x3,
200 .txrestune = 0x2,
201 },
202 .Usb3PhyPort[0] = {
203 .tx_term_ctrl = 0x2,
204 .rx_term_ctrl = 0x2,
205 .tx_vboost_lvl_en = 0x0,
206 .tx_vboost_lvl = 0x5,
207 },
208 .Usb3PhyPort[1] = {
209 .tx_term_ctrl = 0x2,
210 .rx_term_ctrl = 0x2,
211 .tx_vboost_lvl_en = 0x0,
212 .tx_vboost_lvl = 0x5,
213 },
214 .Usb3PhyPort[2] = {
215 .tx_term_ctrl = 0x2,
216 .rx_term_ctrl = 0x2,
217 .tx_vboost_lvl_en = 0x0,
218 .tx_vboost_lvl = 0x5,
219 },
220 .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
221 .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
222 .ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C,
223 .BatteryChargerEnable = 0,
224 .PhyP3CpmP4Support = 0,
225 }"
226
227 device domain 0 on
228 device ref gpp_bridge_2_1 on end # WWAN
229 device ref gpp_bridge_2_2 on # WLAN
230 chip drivers/wifi/generic
231 register "wake" = "GEVENT_8"
232 device pci 00.0 on end
233 end
234 end
235 device ref gpp_bridge_2_3 on end # SD
236 device ref gpp_bridge_2_4 on end # NVMe
237 device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
238 device ref gfx on end # Internal GPU (GFX)
239 device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
240 device ref crypto on end # Crypto Coprocessor
241 device ref xhci_0 on # USB 3.1 (USB0)
242 chip drivers/usb/acpi
243 device ref xhci_0_root_hub on
244 chip drivers/usb/acpi
245 register "desc" = ""USB3 Type-A Port A0 (MLB)""
246 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
247 register "use_custom_pld" = "true"
248 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
249 device ref usb3_port2 on end
250 end
251 chip drivers/usb/acpi
252 register "desc" = ""USB3 Type-A Port A1 (DB)""
253 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
254 register "use_custom_pld" = "true"
255 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
256 register "group" = "ACPI_PLD_GROUP(1, 2)"
257 device ref usb3_port3 on
258 probe DAUGHTERBOARD DB_B
259 end
260 end
261 chip drivers/usb/acpi
262 register "desc" = ""USB3 WWAN""
263 register "type" = "UPC_TYPE_INTERNAL"
264 register "has_power_resource" = "true"
265 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_6)"
266 register "enable_delay_ms" = "20"
267 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_11)"
268 register "reset_off_delay_ms" = "20"
269 device ref usb3_port3 on
270 probe WWAN WWAN_FM101GL
271 end
272 end
273 chip drivers/usb/acpi
274 register "desc" = ""USB2 Type-A Port A0 (MLB)""
275 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
276 register "use_custom_pld" = "true"
277 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
278 device ref usb2_port2 on end
279 end
280 chip drivers/usb/acpi
281 register "desc" = ""USB2 Type-A Port A1 (DB)""
282 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
283 register "use_custom_pld" = "true"
284 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
285 device ref usb2_port3 on end
286 end
287 chip drivers/usb/acpi
288 register "desc" = ""User-Facing Camera""
289 register "type" = "UPC_TYPE_INTERNAL"
290 device ref usb2_port4 on end
291 end
292 chip drivers/usb/acpi
293 register "desc" = ""World-Facing Camera""
294 register "type" = "UPC_TYPE_INTERNAL"
295 device ref usb2_port5 on end
296 end
297 chip drivers/usb/acpi
298 register "desc" = ""Bluetooth""
299 register "type" = "UPC_TYPE_INTERNAL"
300 register "has_power_resource" = "true"
301 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_154)"
302 register "enable_delay_ms" = "500"
303 register "enable_off_delay_ms" = "200"
304 register "use_gpio_for_status" = "true"
305 device ref usb2_port6 on end
306 end
307 end
308 end
309 end
310 device ref acp on end # Audio Processor (ACP)
311 device ref mp2 on end # Sensor Fusion Hub (MP2)
312 end
313 device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
314 device ref usb4_xhci_0 on
315 chip drivers/usb/acpi
316 register "type" = "UPC_TYPE_HUB"
317 device ref usb4_xhci_0_root_hub on
318 chip drivers/usb/acpi
319 register "desc" = ""USB4 Type-C Port C0 (MLB)""
320 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
321 register "use_custom_pld" = "true"
322 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
323 device ref usb3_port0 on end
324 end
325 chip drivers/usb/acpi
326 register "desc" = ""USB4 Type-C Port C0 (MLB)""
327 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
328 register "use_custom_pld" = "true"
329 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
330 device ref usb2_port0 on end
331 end
332 end
333 end
334 end
335 device ref usb4_xhci_1 on
336 chip drivers/usb/acpi
337 register "type" = "UPC_TYPE_HUB"
338 device ref usb4_xhci_1_root_hub on
339 chip drivers/usb/acpi
340 register "desc" = ""USB4 Type-C Port C1 (MLB)""
341 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
342 register "use_custom_pld" = "true"
343 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))"
344 device ref usb3_port1 on end
345 end
346 chip drivers/usb/acpi
347 register "desc" = ""USB2 Type-C Port C1 (MLB)""
348 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
349 register "use_custom_pld" = "true"
350 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))"
351 device ref usb2_port1 on end
352 end
353 end
354 end
355 end
356 end
357 device ref iommu on end
358 device ref lpc_bridge on
359 chip ec/google/chromeec
360 device pnp 0c09.0 alias chrome_ec on end
361 end
362 end
363 end # domain
364 device ref uart_0 on end # UART0
365 device ref i2c_0 on end
366 device ref i2c_1 on end
367 device ref i2c_2 hidden
368 chip drivers/i2c/tpm
369 register "hid" = ""GOOG0005""
370 register "desc" = ""Ti50 TPM""
371 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_84)"
372 device i2c 50 alias ti50 on end
373 end
374 end
375 device ref i2c_3 on end
376 end # chip soc/amd/phoenix
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