1 chip soc
/intel
/apollolake
3 register
"pcie_rp_clkreq_pin[0]" = "2" # PCIe slot
2
4 register
"pcie_rp_clkreq_pin[1]" = "3" # Wifi
+BT M2 slot
5 register
"pcie_rp_clkreq_pin[2]" = "0" # PCIe slot
1
6 register
"pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
7 register
"pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
8 register
"pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
11 device pci
00.0 on
end #
- Host Bridge
12 device pci
00.1 on
end #
- DPTF
13 device pci
00.2 on
end #
- NPK
14 device pci
02.0 on
end #
- Gen
15 device pci
03.0 on
end #
- Iunit
16 device pci
0d
.0 on
end #
- P2SB
17 device pci
0d
.1 on
end #
- PMC
18 device pci
0d
.2 on
end #
- SPI
19 device pci
0d
.3 on
end #
- Shared SRAM
20 device pci
0e
.0 on
end #
- Audio
21 device pci
0f
.0 on
end #
- CSE
22 device pci
11.0 on
end #
- ISH
23 device pci
12.0 on #
- SATA
24 register
"sata_ports_enable[0]" = "1"
25 register
"sata_ports_enable[1]" = "1"
27 device pci
13.0 on
end #
- PCIe
-A
0
28 device pci
13.2 on
end #
- Onboard Lan
29 device pci
13.3 on
end #
- PCIe
-A
3
30 device pci
14.0 on
end #
- PCIe
-B
0
31 device pci
14.1 on
end #
- Onboard M2 Slot
(Wifi
/BT
)
32 device pci
15.0 on
end #
- XHCI
33 device pci
15.1 on
end #
- XDCI
34 device pci
16.0 on
end #
- I2C
0
35 device pci
16.1 on
end #
- I2C
1
36 device pci
16.2 on
end #
- I2C
2
37 device pci
16.3 on
end #
- I2C
3
38 device pci
17.0 on
end #
- I2C
4
39 device pci
17.1 on
end #
- I2C
5
40 device pci
17.2 on
end #
- I2C
6
41 device pci
17.3 on
end #
- I2C
7
42 device pci
18.0 on
end #
- UART
0
43 device pci
18.1 on
end #
- UART
1
44 device pci
18.2 on
end #
- UART
2
45 device pci
18.3 on
end #
- UART
3
46 device pci
19.0 on
end #
- SPI
0
47 device pci
19.1 on
end #
- SPI
1
48 device pci
19.2 on
end #
- SPI
2
49 device pci
1a
.0 on
end #
- PWM
50 device pci
1b
.0 on
end #
- SDCARD
51 device pci
1c
.0 on
end #
- eMMC
52 device pci
1e
.0 on
end #
- SDIO
53 device pci
1f
.0 on
end #
- LPC
54 device pci
1f
.1 on
end #
- SMBUS