src/mainboard/intel/emeraldlake2/chromeos.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootmode.h>
   4 #include <boot/coreboot_tables.h>
   5 #include <device/device.h>
   6 #include <southbridge/intel/bd82x6x/pch.h>
   7 #include <southbridge/intel/common/gpio.h>
   8 #include <types.h>
   9 #include <vendorcode/google/chromeos/chromeos.h>
  10 #include "onboard.h"
  11
  12 void fill_lb_gpios(struct lb_gpios *gpios)
  13 {
  14         struct lb_gpio chromeos_gpios[] = {
  15                 /* Recovery: GPIO22 */
  16                 {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"},
  17
  18                 /* Hard code the lid switch GPIO to open. */
  19                 {-1, ACTIVE_HIGH, 1, "lid"},
  20
  21                 /* Power Button */
  22                 {-1, ACTIVE_HIGH, 0, "power"},
  23
  24                 /* Did we load the VGA option ROM? */
  25                 {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
  26         };
  27         lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
  28 }
  29
  30 int get_recovery_mode_switch(void)
  31 {
  32         /* Recovery: GPIO22, active low */
  33         return !get_gpio(GPIO_REC_MODE);
  34 }
  35
  36 int get_write_protect_state(void)
  37 {
  38         /* Write protect is active low, so invert it here */
  39         return !get_gpio(GPIO_SPI_WP);
  40 }
  41
  42 static const struct cros_gpio cros_gpios[] = {
  43         CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
  44         CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
  45 };
  46
  47 DECLARE_CROS_GPIOS(cros_gpios);