src/mainboard/intel/glkrvp/dsdt.asl

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <variant/ec.h>
   4 #include <variant/gpio.h>
   5
   6 #include <acpi/acpi.h>
   7 DefinitionBlock(
   8         "dsdt.aml",
   9         "DSDT",
  10         ACPI_DSDT_REV_2,
  11         OEM_ID,
  12         ACPI_TABLE_CREATOR,
  13         0x20110725
  14 )
  15 {
  16         #include <acpi/dsdt_top.asl>
  17         #include <soc/intel/apollolake/acpi/globalnvs.asl>
  18         #include <cpu/intel/common/acpi/cpu.asl>
  19
  20         Scope (\_SB) {
  21                 Device (PCI0)
  22                 {
  23                         #include <soc/intel/apollolake/acpi/northbridge.asl>
  24                         #include <soc/intel/apollolake/acpi/southbridge.asl>
  25                         #include <soc/intel/apollolake/acpi/pch_hda.asl>
  26                 }
  27         }
  28
  29         #include <southbridge/intel/common/acpi/sleepstates.asl>
  30
  31         /* ChromeOS Embedded Controller */
  32         Scope (\_SB.PCI0.LPCB)
  33         {
  34                 /* ACPI code for EC SuperIO functions */
  35                 #include <ec/google/chromeec/acpi/superio.asl>
  36                 /* ACPI code for EC functions */
  37                 #include <ec/google/chromeec/acpi/ec.asl>
  38         }
  39
  40         /* Dynamic Platform Thermal Framework */
  41         Scope (\_SB)
  42         {
  43                 /* Per board variant specific definitions. */
  44                 #include <variant/acpi/dptf.asl>
  45                 /* Include soc specific DPTF changes */
  46                 #include <soc/intel/apollolake/acpi/dptf.asl>
  47                 /* Include common dptf ASL files */
  48                 #include <soc/intel/common/acpi/dptf/dptf.asl>
  49         }
  50 }