src/mainboard/intel/kunimitsu/devicetree.cb

   1 chip soc/intel/skylake
   2
   3         # Enable deep Sx states
   4         register "deep_s5_enable_ac" = "1"
   5         register "deep_s5_enable_dc" = "1"
   6         register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
   7
   8         # GPE configuration
   9         # Note that GPE events called out in ASL code rely on this
  10         # route. i.e. If this route changes then the affected GPE
  11         # offset bits also need to be changed.
  12         register "gpe0_dw0" = "GPP_B"
  13         register "gpe0_dw1" = "GPP_D"
  14         register "gpe0_dw2" = "GPP_E"
  15
  16         # Enable DPTF
  17         register "dptf_enable" = "1"
  18
  19         # FSP Configuration
  20         register "DspEnable" = "1"
  21         register "IoBufferOwnership" = "3"
  22         register "ScsEmmcHs400Enabled" = "1"
  23         register "SkipExtGfxScan" = "1"
  24         register "SaGv" = "SaGv_Enabled"
  25
  26         # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
  27         # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
  28         register "PmConfigSlpS3MinAssert" = "0x02"
  29
  30         # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
  31         register "PmConfigSlpS4MinAssert" = "0x04"
  32
  33         # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
  34         register "PmConfigSlpSusMinAssert" = "0x03"
  35
  36         # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
  37         register "PmConfigSlpAMinAssert" = "0x03"
  38
  39
  40         # VR Settings Configuration for 4 Domains
  41         #+----------------+-----------+-----------+-------------+----------+
  42         #| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
  43         #+----------------+-----------+-----------+-------------+----------+
  44         #| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
  45         #| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
  46         #| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
  47         #| Psi3Enable     | 1         | 1         | 1           | 1        |
  48         #| Psi4Enable     | 1         | 1         | 1           | 1        |
  49         #| ImonSlope      | 0         | 0         | 0           | 0        |
  50         #| ImonOffset     | 0         | 0         | 0           | 0        |
  51         #| IccMax         | 7A        | 34A       | 35A         | 35A      |
  52         #| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
  53         #+----------------+-----------+-----------+-------------+----------+
  54         register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
  55                 .vr_config_enable = 1,
  56                 .psi1threshold = VR_CFG_AMP(20),
  57                 .psi2threshold = VR_CFG_AMP(4),
  58                 .psi3threshold = VR_CFG_AMP(1),
  59                 .psi3enable = 1,
  60                 .psi4enable = 1,
  61                 .imon_slope = 0x0,
  62                 .imon_offset = 0x0,
  63                 .icc_max = VR_CFG_AMP(7),
  64                 .voltage_limit = 1520,
  65         }"
  66
  67         register "domain_vr_config[VR_IA_CORE]" = "{
  68                 .vr_config_enable = 1,
  69                 .psi1threshold = VR_CFG_AMP(20),
  70                 .psi2threshold = VR_CFG_AMP(5),
  71                 .psi3threshold = VR_CFG_AMP(1),
  72                 .psi3enable = 1,
  73                 .psi4enable = 1,
  74                 .imon_slope = 0x0,
  75                 .imon_offset = 0x0,
  76                 .icc_max = VR_CFG_AMP(34),
  77                 .voltage_limit = 1520,
  78         }"
  79
  80         register "domain_vr_config[VR_GT_UNSLICED]" = "{
  81                 .vr_config_enable = 1,
  82                 .psi1threshold = VR_CFG_AMP(20),
  83                 .psi2threshold = VR_CFG_AMP(5),
  84                 .psi3threshold = VR_CFG_AMP(1),
  85                 .psi3enable = 1,
  86                 .psi4enable = 1,
  87                 .imon_slope = 0x0,
  88                 .imon_offset = 0x0,
  89                 .icc_max = VR_CFG_AMP(35),
  90                 .voltage_limit = 1520,
  91         }"
  92
  93         register "domain_vr_config[VR_GT_SLICED]" = "{
  94                 .vr_config_enable = 1,
  95                 .psi1threshold = VR_CFG_AMP(20),
  96                 .psi2threshold = VR_CFG_AMP(5),
  97                 .psi3threshold = VR_CFG_AMP(1),
  98                 .psi3enable = 1,
  99                 .psi4enable = 1,
 100                 .imon_slope = 0x0,
 101                 .imon_offset = 0x0,
 102                 .icc_max = VR_CFG_AMP(35),
 103                 .voltage_limit = 1520,
 104         }"
 105
 106         register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"  # I2C4 is 1.8V
 107
 108         # Must leave UART0 enabled or SD/eMMC will not work as PCI
 109         register "SerialIoDevMode" = "{
 110                 [PchSerialIoIndexI2C0]  = PchSerialIoPci,
 111                 [PchSerialIoIndexI2C1]  = PchSerialIoPci,
 112                 [PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
 113                 [PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
 114                 [PchSerialIoIndexI2C4]  = PchSerialIoPci,
 115                 [PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
 116                 [PchSerialIoIndexSpi0]  = PchSerialIoDisabled,
 117                 [PchSerialIoIndexSpi1]  = PchSerialIoDisabled,
 118                 [PchSerialIoIndexUart0] = PchSerialIoPci,
 119                 [PchSerialIoIndexUart1] = PchSerialIoDisabled,
 120                 [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
 121         }"
 122
 123         # PL2 override 25W
 124         register "power_limits_config" = "{
 125                 .tdp_pl2_override = 25,
 126         }"
 127
 128         # Send an extra VR mailbox command for the PS4 exit issue
 129         register "SendVrMbxCmd" = "2"
 130
 131         # Use default SD card detect GPIO configuration
 132         register "sdcard_cd_gpio" = "GPP_A7"
 133
 134         device domain 0 on
 135                 device ref igpu         on  end
 136                 device ref sa_thermal   on  end
 137                 device ref south_xhci   on
 138                         register "usb2_ports" = "{
 139                                 [0] = USB2_PORT_TYPE_C(OC0),    /* Type-C Port 1 */
 140                                 [1] = USB2_PORT_TYPE_C(OC1),    /* Type-C Port 2 */
 141                                 [2] = USB2_PORT_MID(OC_SKIP),   /* Bluetooth */
 142                                 [4] = USB2_PORT_MID(OC2),       /* Type-A Port (card) */
 143                                 [6] = USB2_PORT_FLEX(OC_SKIP),  /* Camera */
 144                                 [8] = USB2_PORT_LONG(OC3),      /* Type-A Port (board) */
 145                         }"
 146
 147                         register "usb3_ports" = "{
 148                                 [0] = USB3_PORT_DEFAULT(OC0),   /* Type-C Port 1 */
 149                                 [1] = USB3_PORT_DEFAULT(OC1),   /* Type-C Port 2 */
 150                                 [2] = USB3_PORT_DEFAULT(OC2),   /* Type-A Port (card) */
 151                                 [3] = USB3_PORT_DEFAULT(OC3),   /* Type-A Port (board) */
 152                         }"
 153                 end
 154                 device ref thermal      on  end
 155                 device ref i2c0         on
 156                         chip drivers/i2c/generic
 157                                 register "hid" = ""ELAN0001""
 158                                 register "desc" = ""ELAN Touchscreen""
 159                                 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
 160                                 device i2c 10 on end
 161                         end
 162                 end
 163                 device ref i2c1         on
 164                         chip drivers/i2c/generic
 165                                 register "hid" = ""ELAN0000""
 166                                 register "desc" = ""ELAN Touchpad""
 167                                 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
 168                                 register "wake" = "GPE0_DW0_05"
 169                                 device i2c 15 on end
 170                         end
 171                 end
 172                 device ref heci1        on  end
 173                 device ref uart2        on  end
 174                 device ref i2c4         on
 175                         chip drivers/i2c/nau8825
 176                                 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)"
 177                                 register "jkdet_enable" = "1"
 178                                 register "jkdet_pull_enable" = "1"
 179                                 register "jkdet_pull_up" = "1"
 180                                 register "jkdet_polarity" = "1"      # ActiveLow
 181                                 register "vref_impedance" = "2"      # 125kOhm
 182                                 register "micbias_voltage" = "6"     # 2.754
 183                                 register "sar_threshold_num" = "4"
 184                                 register "sar_threshold[0]" = "0x08"
 185                                 register "sar_threshold[1]" = "0x12"
 186                                 register "sar_threshold[2]" = "0x26"
 187                                 register "sar_threshold[3]" = "0x73"
 188                                 register "sar_hysteresis" = "0"
 189                                 register "sar_voltage" = "6"
 190                                 register "sar_compare_time" = "1"     # 1us
 191                                 register "sar_sampling_time" = "1"    # 4us
 192                                 register "short_key_debounce" = "3"   # 30ms
 193                                 register "jack_insert_debounce" = "7" # 512ms
 194                                 register "jack_eject_debounce" = "0"
 195                                 device i2c 1a on end
 196                         end
 197                         chip drivers/i2c/generic
 198                                 register "hid" = ""INT343B""
 199                                 register "desc" = ""SSM4567 Left Speaker Amp""
 200                                 register "uid" = "0"
 201                                 register "device_present_gpio" = "GPP_E3"
 202                                 device i2c 34 on end
 203                         end
 204                         chip drivers/i2c/generic
 205                                 register "hid" = ""INT343B""
 206                                 register "desc" = ""SSM4567 Right Speaker Amp""
 207                                 register "uid" = "1"
 208                                 register "device_present_gpio" = "GPP_E3"
 209                                 device i2c 35 on end
 210                         end
 211                 end
 212                 device ref pcie_rp1     on
 213                         register "PcieRpEnable[0]" = "1"
 214                         register "PcieRpClkReqSupport[0]" = "1"
 215                         register "PcieRpClkReqNumber[0]" = "1"
 216                         chip drivers/wifi/generic
 217                                 register "wake" = "GPE0_DW0_16"
 218                                 device pci 00.0 on end
 219                         end
 220                 end
 221                 device ref pcie_rp5     on
 222                         register "PcieRpEnable[4]" = "1"
 223                         register "PcieRpClkReqSupport[4]" = "1"
 224                         register "PcieRpClkReqNumber[4]" = "2"
 225                 end
 226                 device ref uart0        on end
 227                 device ref emmc         on end
 228                 device ref sdxc         on end
 229                 device ref lpc_espi     on
 230                         # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
 231                         register "gen1_dec" = "0x00fc0801"
 232                         register "gen2_dec" = "0x000c0201"
 233
 234                         chip drivers/pc80/tpm
 235                                 device pnp 0c31.0 on end
 236                         end
 237                         chip ec/google/chromeec
 238                                 device pnp 0c09.0 on end
 239                         end
 240                 end
 241                 device ref hda on
 242                         chip drivers/generic/max98357a
 243                                 register "hid" = ""MX98357A""
 244                                 register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)"
 245                                 register "device_present_gpio" = "GPP_E3"
 246                                 register "device_present_gpio_invert" = "1"
 247                                 device generic 0 on end
 248                         end
 249                 end
 250                 device ref smbus        on end
 251                 device ref fast_spi     on end
 252         end
 253 end