src/mainboard/intel/minnow3/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include "gpio.h"
   4
   5 /*
   6  * GPIO Pad configuration in ramstage.
   7  */
   8 static const struct pad_config gpio_table_config[] = {
   9         PAD_CFG_GPO(GPIO_0, 1, DEEP),
  10         PAD_CFG_GPO(GPIO_1, 1, DEEP),
  11         PAD_CFG_NF(GPIO_2, DN_20K, DEEP, NF1),
  12         PAD_CFG_NF(GPIO_3, DN_20K, DEEP, NF1),
  13         PAD_CFG_NF(GPIO_4, DN_20K, DEEP, NF1),
  14         PAD_CFG_NF(GPIO_5, DN_20K, DEEP, NF1),
  15         PAD_CFG_NF(GPIO_6, DN_20K, DEEP, NF1),
  16         PAD_CFG_NF(GPIO_7, DN_20K, DEEP, NF1),
  17         PAD_CFG_NF(GPIO_8, DN_20K, DEEP, NF1),
  18         PAD_CFG_NF(GPIO_9, DN_20K, DEEP, NF1),
  19         PAD_CFG_GPI(GPIO_10, DN_20K, DEEP),
  20         PAD_CFG_NF(GPIO_11, DN_20K, DEEP, NF1),
  21         PAD_CFG_NF(GPIO_12, DN_20K, DEEP, NF1),
  22         PAD_CFG_NF(GPIO_13, DN_20K, DEEP, NF1),
  23         PAD_CFG_NF(GPIO_14, DN_20K, DEEP, NF1),
  24         PAD_CFG_GPO(GPIO_15, 1, DEEP),
  25         PAD_CFG_GPI(GPIO_16, UP_20K, DEEP),
  26         PAD_CFG_NF(GPIO_17, UP_20K, DEEP, NF1),
  27         PAD_CFG_NF(GPIO_18, UP_20K, DEEP, NF1),
  28         PAD_CFG_NF(GPIO_19, UP_20K, DEEP, NF1),
  29         PAD_CFG_NF(GPIO_20, DN_20K, DEEP, NF1),
  30         PAD_CFG_NF(GPIO_21, DN_20K, DEEP, NF1),
  31         PAD_CFG_GPO(GPIO_22, 1, DEEP),/* Power Enable */
  32         PAD_CFG_GPO(GPIO_23, 1, DEEP),/* LB USB Power */
  33         PAD_CFG_NF(GPIO_24, DN_20K, DEEP, NF5),/* SATA_DEVSLP0 */
  34         PAD_CFG_GPI(GPIO_25, DN_20K, DEEP),/* OSS MD/DA SCI */
  35         PAD_CFG_NF(GPIO_26, DN_20K, DEEP, NF5),/* SATA_LEDN */
  36         PAD_CFG_GPO(GPIO_27, 1, DEEP),/* DFU */
  37         PAD_CFG_NF(GPIO_28, DN_20K, DEEP, NF2),
  38         PAD_CFG_NF(GPIO_29, DN_20K, DEEP, NF2),
  39         PAD_CFG_NF(GPIO_30, DN_20K, DEEP, NF1),
  40         PAD_CFG_NF(GPIO_31, DN_20K, DEEP, NF5),/* SUSCLK1 */
  41         PAD_CFG_NF(GPIO_32, DN_20K, DEEP, NF5),
  42         PAD_CFG_NF(GPIO_33, DN_20K, DEEP, NF5),/* SUSCLK3 */
  43         /* PWM */
  44         PAD_CFG_NF(GPIO_34, DN_20K, DEEP, NF1),/* PWM */
  45         PAD_CFG_GPO(GPIO_35, 1, DEEP),/* Power Enable */
  46         PAD_CFG_NF(GPIO_36, DN_20K, DEEP, NF1),/* PWM */
  47         PAD_CFG_NF(GPIO_37, NONE, DEEP, NF1),/* Reset */
  48         /* UART */
  49         PAD_CFG_NF(GPIO_38, UP_20K, DEEP, NF1),/* LPSS_UART0_RXD */
  50         PAD_CFG_NF(GPIO_39, UP_20K, DEEP, NF1),/* LPSS_UART0_TXD */
  51         PAD_CFG_NF(GPIO_40, UP_20K, DEEP, NF1),/* LPSS_UART0_RTS_B */
  52         PAD_CFG_NF(GPIO_41, UP_20K, DEEP, NF1),/* LPSS_UART0_CTS_B */
  53         PAD_CFG_NF(GPIO_42, UP_20K, DEEP, NF1),/* LPSS_UART1_RXD */
  54         PAD_CFG_NF(GPIO_43, UP_20K, DEEP, NF1),/* LPSS_UART1_TXD */
  55         PAD_CFG_NF(GPIO_44, UP_20K, DEEP, NF1),/* LPSS_UART1_RTS_B */
  56         PAD_CFG_NF(GPIO_45, NONE, DEEP, NF1),/* LPSS_UART1_CTS_B */
  57
  58         PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), /* LPSS_UART2_RXD */
  59         PAD_CFG_NF(GPIO_47, UP_20K, DEEP, NF1), /* LPSS_UART2_TXD */
  60
  61         PAD_CFG_GPI(GPIO_48, UP_20K, DEEP),/* LPSS_UART2_RTS_B */
  62         PAD_CFG_NF(GPIO_49, UP_20K, DEEP, NF1),/* LPSS_UART2_CTS_B */
  63         PAD_CFG_GPO(GPIO_62, 0, DEEP),/* GP_CAMERASB00 */
  64         PAD_CFG_GPO(GPIO_63, 0, DEEP),/* GP_CAMERASB01 */
  65         PAD_CFG_GPO(GPIO_64, 0, DEEP),/* GP_CAMERASB02 */
  66         PAD_CFG_GPO(GPIO_65, 0, DEEP),/* GP_CAMERASB03 */
  67         PAD_CFG_GPO(GPIO_66, 0, DEEP),/* GP_CAMERASB04 */
  68         PAD_CFG_GPO(GPIO_67, 0, DEEP),/* GP_CAMERASB05 */
  69         PAD_CFG_GPO(GPIO_68, 0, DEEP),/* GP_CAMERASB06 */
  70         PAD_CFG_GPO(GPIO_69, 0, DEEP),/* GP_CAMERASB07 */
  71         PAD_CFG_GPO(GPIO_70, 0, DEEP),/* GP_CAMERASB08 */
  72         PAD_CFG_GPO(GPIO_71, 0, DEEP),/* GP_CAMERASB09 */
  73         PAD_CFG_GPO(GPIO_72, 0, DEEP),/* GP_CAMERASB10 */
  74         PAD_CFG_GPO(GPIO_73, 0, DEEP),/* GP_CAMERASB11 */
  75         PAD_CFG_NF(TCK, DN_20K, DEEP, NF1), /* TCK */
  76         PAD_CFG_NF(TRST_B, DN_20K, DEEP, NF1),/* TRST_B */
  77         PAD_CFG_NF(TMS, UP_20K, DEEP, NF1),/* TMS */
  78         PAD_CFG_NF(TDI, UP_20K, DEEP, NF1),/* TDI */
  79         PAD_CFG_NF(CX_PMODE, NONE, DEEP, NF1),/* CX_PMODE */
  80         PAD_CFG_NF(CX_PREQ_B, UP_20K, DEEP, NF1),/* CX_PREQ_B */
  81         PAD_CFG_NF(JTAGX, UP_20K, DEEP, NF1),/* JTAGX */
  82         PAD_CFG_NF(CX_PRDY_B, UP_20K, DEEP, NF1),/* CX_PRDY_B */
  83         PAD_CFG_NF(TDO, UP_20K, DEEP, NF1),/* TDO */
  84         PAD_CFG_GPI(CNV_BRI_DT, DN_20K, DEEP),/* CNV_BRI_DT */
  85         PAD_CFG_GPI(CNV_BRI_RSP, DN_20K, DEEP),/* CNV_BRI_RSP */
  86         PAD_CFG_GPI(CNV_RGI_DT, DN_20K, DEEP),/* CNV_RGI_DT */
  87         PAD_CFG_GPI(CNV_RGI_RSP, DN_20K, DEEP),/* CNV_RGI_RSP */
  88         PAD_CFG_NF(SVID0_ALERT_B, NONE, DEEP, NF1),/* SVID0_ALERT_B */
  89         PAD_CFG_NF(SVID0_DATA, UP_20K, DEEP, NF1),/* SVID0_DATA */
  90         PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1),/* SVID0_CLK */
  91
  92         /* North West Community */
  93         PAD_CFG_NF(GPIO_187, UP_20K, DEEP, NF1),/* DDI0_CTRL_DATA */
  94         PAD_CFG_NF(GPIO_188, UP_20K, DEEP, NF1),/* DDI0_CTRL_CLK */
  95         PAD_CFG_NF(GPIO_189, UP_20K, DEEP, NF1),/* DDI1_CTRL_DATA */
  96         PAD_CFG_NF(GPIO_190, UP_20K, DEEP, NF1),/* DDI1_CTRL_CLK */
  97         PAD_CFG_NF(GPIO_191, DN_20K, DEEP, NF1),/* DBI_SDA */
  98         PAD_CFG_NF(GPIO_192, DN_20K, DEEP, NF1),/* DBI_SCL */
  99         PAD_CFG_NF(GPIO_193, DN_20K, DEEP, NF1),/* DISP0_VDDEN */
 100         PAD_CFG_NF(GPIO_194, DN_20K, DEEP, NF1),/* DISP0_BKLTEN */
 101         PAD_CFG_NF(GPIO_195, DN_20K, DEEP, NF1),/* DISP0_BLTCTL */
 102         PAD_CFG_GPO(GPIO_196, 1, DEEP),/* DISP1_VDDEN */
 103         PAD_CFG_GPO(GPIO_197, 1, DEEP),/* DISP1_BKLTEN */
 104         PAD_CFG_GPO(GPIO_198, 1, DEEP),/* DISP1_BLTCTL */
 105         PAD_CFG_NF(GPIO_199, DN_20K, DEEP, NF2),/* HDMI_HPD */
 106         PAD_CFG_NF(GPIO_200, DN_20K, DEEP, NF2),/* EDP_HPD */
 107         PAD_CFG_NF(GPIO_201, DN_20K, DEEP, NF1),/* DISP_INTD_TE1 */
 108         PAD_CFG_NF(GPIO_202, DN_20K, DEEP, NF1),/* DISP_INTD_TE2 */
 109         PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1),/* HOST_USB_OC_N */
 110         PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1),/* OTG_USB_OC_N */
 111         PAD_CFG_NF(PMC_SPI_FS0, UP_20K, DEEP, NF1),/* PMC_SPI_FS0 */
 112         PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2),/* PMC_SPI_FS1 */
 113         PAD_CFG_NF(PMC_SPI_FS2, UP_20K, DEEP, NF1),/* PMC_SPI_FS2 */
 114         PAD_CFG_NF(PMC_SPI_RXD, DN_20K, DEEP, NF1),/* PMC_SPI_RXD */
 115         PAD_CFG_NF(PMC_SPI_TXD, DN_20K, DEEP, NF1),/* PMC_SPI_TXD */
 116         PAD_CFG_NF(PMC_SPI_CLK, DN_20K, DEEP, NF1),/* PMC_SPI_CLK */
 117         PAD_CFG_GPO(PMIC_PWRGOOD, 1, DEEP),/* PMIC_PWRGOOD */
 118         PAD_CFG_GPI(PMIC_RESET_B, NONE, DEEP),/* PMIC_RESET_B */
 119         PAD_CFG_GPO(GPIO_213, 0xFF, DEEP),/* PMIC_SDWN_B */
 120         PAD_CFG_GPO(GPIO_214, 1, DEEP),/* PMIC_BCUDISW2 */
 121         PAD_CFG_GPO(GPIO_215, 1, DEEP),/* PMIC_BCUDISCRIT */
 122         PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1),/* PMIC_THERMTRIP_B */
 123         PAD_CFG_GPO(PMIC_STDBY, 1, DEEP),/* PMIC_STDBY */
 124         PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1),/* PROCHOT_B */
 125         PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1),/* PMIC_I2C_SCL */
 126         PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1),/* PMIC_I2C_SDA */
 127
 128         PAD_CFG_NF(GPIO_74, DN_20K, DEEP, NF1),/* AVS_I2S1_MCLK */
 129         PAD_CFG_NF(GPIO_75, DN_20K, DEEP, NF1),/* AVS_I2S1_BCLK */
 130         PAD_CFG_GPO(GPIO_76, 1, DEEP),/* AVS_I2S1_WS_SYNC */
 131         PAD_CFG_GPI(GPIO_77, DN_20K, DEEP),/* AVS_I2S1_SDI */
 132         PAD_CFG_GPI(GPIO_78, DN_20K, DEEP),/* AVS_I2S1_SDO */
 133         PAD_CFG_NF(GPIO_79, DN_20K, DEEP, NF1),/* AVS_M_CLK_A1 */
 134         PAD_CFG_NF(GPIO_80, DN_20K, DEEP, NF1),/* AVS_M_CLK_B1 */
 135         PAD_CFG_NF(GPIO_81, DN_20K, DEEP, NF1),/* AVS_M_DATA_1 */
 136         PAD_CFG_NF(GPIO_82, DN_20K, DEEP, NF1),/* AVS_M_CLK_AB2 */
 137         PAD_CFG_NF(GPIO_83, DN_20K, DEEP, NF1),/* AVS_M_DATA_2 */
 138         PAD_CFG_NF(GPIO_84, DN_20K, DEEP, NF2),/* AVS_I2S2_MCLK */
 139         PAD_CFG_NF(GPIO_85, DN_20K, DEEP, NF1),/* AVS_I2S2_BCLK */
 140         PAD_CFG_NF(GPIO_86, DN_20K, DEEP, NF1),/* AVS_I2S2_WS_SYNC */
 141         PAD_CFG_NF(GPIO_87, DN_20K, DEEP, NF1),/* AVS_I2S2_SDI */
 142         PAD_CFG_NF(GPIO_88, DN_20K, DEEP, NF1),/* AVS_I2S2_SDO */
 143         PAD_CFG_NF(GPIO_89, DN_20K, DEEP, NF1),/* AVS_I2S3_BCLK */
 144         PAD_CFG_NF(GPIO_90, DN_20K, DEEP, NF1),/* AVS_I2S3_WS_SYNC */
 145         PAD_CFG_NF(GPIO_91, DN_20K, DEEP, NF1),/* AVS_I2S3_SDI */
 146         PAD_CFG_NF(GPIO_92, DN_20K, DEEP, NF1),/* AVS_I2S3_SDO */
 147         PAD_CFG_NF(GPIO_97, NONE, DEEP, NF1),/* FST_SPI_CS0_B */
 148         PAD_CFG_NF(GPIO_98, NONE, DEEP, NF1),/* FST_SPI_CS1_B */
 149         PAD_CFG_NF(GPIO_99, NONE, DEEP, NF1),/* FST_SPI_MOSI_IO0 */
 150         PAD_CFG_NF(GPIO_100, NONE, DEEP, NF1),/* FST_SPI_MISO_IO1 */
 151         PAD_CFG_NF(GPIO_101, NONE, DEEP, NF1),/* FST_SPI_IO2 */
 152         PAD_CFG_NF(GPIO_102, NONE, DEEP, NF1),/* FST_SPI_IO3 */
 153         PAD_CFG_NF(GPIO_103, NONE, DEEP, NF1),/* FST_SPI_CLK */
 154         PAD_CFG_NF(FST_SPI_CLK_FB, NONE, DEEP, NF1),/* FST_SPI_CLK_FB */
 155         PAD_CFG_NF(GPIO_104, DN_20K, DEEP, NF1),/* GP_SSP_0_CLK */
 156         PAD_CFG_NF(GPIO_105, DN_20K, DEEP, NF1),/* GP_SSP_0_FS0 */
 157         PAD_CFG_NF(GPIO_106, DN_20K, DEEP, NF3),/* GP_SSP_0_FS1 */
 158         PAD_CFG_NF(GPIO_109, DN_20K, DEEP, NF1),/* GP_SSP_0_RXD */
 159         PAD_CFG_NF(GPIO_110, DN_20K, DEEP, NF1),/* GP_SSP_0_TXD */
 160         PAD_CFG_GPI(GPIO_111, DN_20K, DEEP),/* GP_SSP_1_CLK */
 161         PAD_CFG_NF(GPIO_112, DN_20K, DEEP, NF2),/* GP_SSP_1_FS0 */
 162         PAD_CFG_GPI(GPIO_113, DN_20K, DEEP),/* GP_SSP_1_FS1 */
 163         PAD_CFG_NF(GPIO_116, DN_20K, DEEP, NF2),/* GP_SSP_1_RXD */
 164         PAD_CFG_NF(GPIO_117, DN_20K, DEEP, NF2),/* GP_SSP_1_TXD */
 165         PAD_CFG_NF(GPIO_118, DN_20K, DEEP, NF1),/* GP_SSP_2_CLK */
 166         PAD_CFG_NF(GPIO_119, DN_20K, DEEP, NF1),/* GP_SSP_2_FS0 */
 167         PAD_CFG_NF(GPIO_120, DN_20K, DEEP, NF1),/* GP_SSP_2_FS1 */
 168         PAD_CFG_NF(GPIO_121, DN_20K, DEEP, NF1),/* GP_SSP_2_FS2 */
 169         PAD_CFG_NF(GPIO_122, DN_20K, DEEP, NF1),/* GP_SSP_2_RXD */
 170         PAD_CFG_NF(GPIO_123, DN_20K, DEEP, NF1),/* GP_SSP_2_TXD */
 171
 172         /* West Community */
 173         PAD_CFG_NF(GPIO_124, UP_1K, DEEP, NF1),/* LPSS_I2C0_SDA */
 174         PAD_CFG_NF(GPIO_125, UP_1K, DEEP, NF1),/* LPSS_I2C0_SCL */
 175         PAD_CFG_NF(GPIO_126, UP_1K, DEEP, NF1),/* LPSS_I2C1_SDA */
 176         PAD_CFG_NF(GPIO_127, UP_1K, DEEP, NF1),/* LPSS_I2C1_SCL */
 177         PAD_CFG_NF(GPIO_128, UP_1K, DEEP, NF1),/* LPSS_I2C2_SDA */
 178         PAD_CFG_NF(GPIO_129, UP_1K, DEEP, NF1),/* LPSS_I2C2_SCL */
 179         PAD_CFG_NF(GPIO_130, UP_1K, DEEP, NF2),/* LPSS_I2C3_SDA */
 180         PAD_CFG_NF(GPIO_131, UP_1K, DEEP, NF2),/* LPSS_I2C3_SCL */
 181         PAD_CFG_NF(GPIO_132, UP_1K, DEEP, NF1),/* LPSS_I2C4_SDA */
 182         PAD_CFG_NF(GPIO_133, UP_1K, DEEP, NF1),/* LPSS_I2C4_SCL */
 183
 184         PAD_CFG_NF(GPIO_134, UP_20K, DEEP, NF2),/* ISH_I2C0_SDA */
 185         PAD_CFG_NF(GPIO_135, UP_20K, DEEP, NF2),/* ISH_I2C0_SCL */
 186         PAD_CFG_NF(GPIO_136, UP_20K, DEEP, NF2),/* ISH_I2C1_SDA */
 187         PAD_CFG_NF(GPIO_137, UP_20K, DEEP, NF2),/* ISH_I2C1_SCL */
 188
 189         PAD_CFG_NF(GPIO_138, UP_1K, DEEP, NF1),/* LPSS_I2C7_SDA */
 190         PAD_CFG_NF(GPIO_139, UP_1K, DEEP, NF1),/* LPSS_I2C7_SCL */
 191         PAD_CFG_NF(GPIO_146, DN_20K, DEEP, NF3),/* ISH_GPIO_0 */
 192         PAD_CFG_NF(GPIO_147, DN_20K, DEEP, NF3),/* ISH_GPIO_1 */
 193         PAD_CFG_NF(GPIO_148, DN_20K, DEEP, NF3),/* ISH_GPIO_2 */
 194         PAD_CFG_NF(GPIO_149, DN_20K, DEEP, NF3),/* ISH_GPIO_3 */
 195         PAD_CFG_NF(GPIO_150, DN_20K, DEEP, NF2),/* ISH_GPIO_4 */
 196
 197         PAD_CFG_GPO(GPIO_151, 0, DEEP),/* ISH_GPIO_5 */
 198         PAD_CFG_NF(GPIO_152, DN_20K, DEEP, NF2),/* ISH_GPIO_6 */
 199         PAD_CFG_NF(GPIO_153, DN_20K, DEEP, NF1),/* ISH_GPIO_7 */
 200         PAD_CFG_GPO(GPIO_154, 1, DEEP),/* ISH_GPIO_8 */
 201         PAD_CFG_NF(GPIO_155, DN_20K, DEEP, NF2),/* ISH_GPIO_9 */
 202
 203         PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1),/* PCIE_CLKREQ0_B */
 204         PAD_CFG_NF(GPIO_210, DN_20K, DEEP, NF1),/* PCIE_CLKREQ1_B */
 205         PAD_CFG_NF(GPIO_211, DN_20K, DEEP, NF1),/* PCIE_CLKREQ2_B */
 206         PAD_CFG_NF(GPIO_212, DN_20K, DEEP, NF1),/* PCIE_CLKREQ3_B */
 207
 208         PAD_CFG_NF(OSC_CLK_OUT_0, DN_20K, DEEP, NF1),/* OSC_CLK_OUT_0 */
 209         PAD_CFG_NF(OSC_CLK_OUT_1, DN_20K, DEEP, NF1),/* OSC_CLK_OUT_1 */
 210         PAD_CFG_NF(OSC_CLK_OUT_2, DN_20K, DEEP, NF1),/* OSC_CLK_OUT_2 */
 211         PAD_CFG_NF(OSC_CLK_OUT_3, DN_20K, DEEP, NF1),/* OSC_CLK_OUT_3 */
 212         PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP),/* OSC_CLK_OUT_4 */
 213
 214         PAD_CFG_NF(PMU_AC_PRESENT, DN_20K, DEEP, NF1),/*PMU_AC_PRESENT  */
 215         PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1),/* PMU_BATLOW_B */
 216         PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1),/* PMU_PLTRST_B */
 217         PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1),/* PMU_PWRBTN_B */
 218         PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1),/* PMU_RESETBUTTON_B */
 219         PAD_CFG_NF(PMU_SLP_S0_B, NONE, DEEP, NF1),/* PMU_SLP_S0_B */
 220         PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1),/* PMU_SLP_S3_B */
 221         PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1),/* PMU_SLP_S4_B */
 222         PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1),/* PMU_SUSCLK */
 223         PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP),/* PMU_WAKE_B */
 224         PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1),/* SUS_STAT_B */
 225         PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1),/* SUSPWRDNACK */
 226
 227         /* South West Community */
 228         PAD_CFG_NF(GPIO_205, UP_20K, DEEP, NF1),/* PCIE_WAKE0_B */
 229         PAD_CFG_NF(GPIO_206, UP_20K, DEEP, NF1),/* PCIE_WAKE1_B */
 230         PAD_CFG_NF(GPIO_207, UP_20K, DEEP, NF1),/* PCIE_WAKE2_B */
 231         PAD_CFG_NF(GPIO_208, UP_20K, DEEP, NF1),/* PCIE_WAKE3_B */
 232         PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1),/* EMMC0_CLK */
 233         PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1),/* EMMC0_D0 */
 234         PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1),/* EMMC0_D1 */
 235         PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1),/* EMMC0_D2 */
 236         PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1),/* EMMC0_D3 */
 237         PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1),/* EMMC0_D4 */
 238         PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1),/* EMMC0_D5 */
 239         PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1),/* EMMC0_D6 */
 240         PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1),/* EMMC0_D7 */
 241         PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1),/* EMMC0_CMD */
 242         PAD_CFG_NF(GPIO_166, DN_20K, DEEP, NF1),/* SDIO_CLK */
 243         PAD_CFG_NF(GPIO_167, UP_20K, DEEP, NF1),/* SDIO_D0 */
 244         PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1),/* SDIO_D1 */
 245         PAD_CFG_NF(GPIO_169, UP_20K, DEEP, NF1),/* SDIO_D2 */
 246         PAD_CFG_NF(GPIO_170, UP_20K, DEEP, NF1),/* SDIO_D3 */
 247         PAD_CFG_NF(GPIO_171, UP_20K, DEEP, NF1),/* SDIO_CMD */
 248         PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1),/* SDCARD_CLK */
 249         PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1),/* SDCARD_CLK_FB */
 250         PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1),/* SDCARD_D0 */
 251         PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1),/* SDCARD_D1 */
 252         PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1),/* SDCARD_D2 */
 253         PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1),/* SDCARD_D3 */
 254         PAD_CFG_GPI(GPIO_177, NONE, DEEP),/* SDCARD_CD_B */
 255         PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1),/* SDCARD_CMD */
 256         PAD_CFG_GPI(GPIO_186, DN_20K, DEEP),/* SDCARD_LVL_WP */
 257         PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1),/* EMMC0_STROBE */
 258         PAD_CFG_GPO(GPIO_183, 0, DEEP),/* SDIO_PWR_DOWN_B */
 259         PAD_CFG_NF(SMB_ALERTB, UP_20K, DEEP, NF1),/* SMB_ALERTB */
 260
 261         PAD_CFG_NF(SMB_CLK, UP_20K, DEEP, NF1),/* SMB_CLK */
 262         PAD_CFG_NF(SMB_DATA, UP_20K, DEEP, NF1),/* SMB_DATA */
 263         PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),/* LPC_ILB_SERIRQ */
 264         PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1),/*LPC_CLKOUT0  */
 265         PAD_CFG_NF(LPC_CLKOUT1, NONE, DEEP, NF1),/* LPC_CLKOUT1 */
 266         PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),/* LPC_AD0 */
 267         PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),/* LPC_AD1 */
 268         PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),/* LPC_AD2 */
 269         PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),/* LPC_AD3 */
 270         PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),/* LPC_CLKRUNB */
 271         PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1),/* LPC_FRAMEB */
 272 };
 273
 274 const struct pad_config *gpio_table(size_t *num)
 275 {
 276         *num = ARRAY_SIZE(gpio_table_config);
 277         return gpio_table_config;
 278 }
 279
 280 /* GPIOs needed prior to ramstage. */
 281 static const struct pad_config early_gpio_table_config[] = {
 282         PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), /* LPSS_UART2_RXD */
 283         PAD_CFG_NF(GPIO_47, UP_20K, DEEP, NF1), /* LPSS_UART2_TXD */
 284
 285         PAD_CFG_NF(GPIO_134, UP_20K, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */
 286         PAD_CFG_NF(GPIO_135, UP_20K, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */
 287         PAD_CFG_NF(GPIO_136, UP_20K, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */
 288         PAD_CFG_NF(GPIO_137, UP_20K, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */
 289
 290         PAD_CFG_NF(GPIO_0, DN_20K, DEEP, NF1),
 291         PAD_CFG_NF(GPIO_1, DN_20K, DEEP, NF1),
 292         PAD_CFG_NF(GPIO_2, DN_20K, DEEP, NF1),
 293         PAD_CFG_NF(GPIO_3, DN_20K, DEEP, NF1),
 294         PAD_CFG_NF(GPIO_4, DN_20K, DEEP, NF1),
 295         PAD_CFG_NF(GPIO_5, DN_20K, DEEP, NF1),
 296         PAD_CFG_NF(GPIO_6, DN_20K, DEEP, NF1),
 297         PAD_CFG_NF(GPIO_7, DN_20K, DEEP, NF1),
 298         PAD_CFG_NF(GPIO_8, DN_20K, DEEP, NF1),
 299
 300         /* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */
 301         PAD_CFG_NF(GPIO_7, UP_1K, DEEP, NF1),
 302         /* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */
 303         PAD_CFG_NF(GPIO_8, UP_1K, DEEP, NF1),
 304
 305         PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */
 306         PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */
 307         PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */
 308         PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */
 309         PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */
 310
 311         PAD_CFG_NF(GPIO_210, DN_20K, DEEP, NF1), /* CLKREQ# */
 312
 313         PAD_CFG_NF(SMB_CLK, UP_20K, DEEP, NF1),
 314         PAD_CFG_NF(SMB_DATA, UP_20K, DEEP, NF1),
 315         PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
 316         PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1),
 317         PAD_CFG_NF(LPC_CLKOUT1, NONE, DEEP, NF1),
 318         PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),
 319         PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),
 320         PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),
 321         PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),
 322         PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),
 323         PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1),
 324 };
 325
 326 const struct pad_config *early_gpio_table(size_t *num)
 327 {
 328         *num = ARRAY_SIZE(early_gpio_table_config);
 329         return early_gpio_table_config;
 330 }
 331
 332 /* GPIO settings before entering sleep. */
 333 static const struct pad_config sleep_gpio_table_config[] = {
 334 };
 335
 336 const struct pad_config *sleep_gpio_table(size_t *num)
 337 {
 338         *num = ARRAY_SIZE(sleep_gpio_table_config);
 339         return sleep_gpio_table_config;
 340 }