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mb/google/brox/var/jubilant: Disable Tccold Handshake
[coreboot.git] / src / mainboard / msi / ms7d25 / gpio.h
blob2d7e4fbbada3d624f87daa19791f40d1e98aec90
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <soc/gpio.h>
4
5 /* Pad configuration was generated automatically using intelp2m utility */
6 static const struct pad_config gpio_table[] = {
7 /* ------- GPIO Community 0 ------- */
8
9 /* ------- GPIO Group GPP_I ------- */
10
11 /* GPP_I0 - GPIO */
12 PAD_CFG_GPI_TRIG_OWN(GPP_I0, NONE, PLTRST, OFF, ACPI),
13 /* GPP_I1 - DDSP_HPD1 */
14 PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),
15 /* GPP_I2 - DDSP_HPD2 */
16 PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1),
17 /* GPP_I3 - DDSP_HPD3 */
18 PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1),
19 /* GPP_I4 - DDSP_HPD4 */
20 PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1),
21 /* GPP_I5 - DDPB_CTRLCLK */
22 PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1),
23 /* GPP_I6 - DDPB_CTRLDATA */
24 PAD_CFG_NF(GPP_I6, NONE, PLTRST, NF1),
25 /* GPP_I7 - DDPC_CTRLCLK */
26 PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1),
27 /* GPP_I8 - DDPC_CTRLDATA */
28 PAD_CFG_NF(GPP_I8, NONE, PLTRST, NF1),
29 /* GPP_I9 - GPIO */
30 PAD_CFG_GPI_TRIG_OWN(GPP_I9, NONE, PLTRST, OFF, ACPI),
31 /* GPP_I10 - GPIO */
32 PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, PLTRST, OFF, ACPI),
33 /* GPP_I11 - USB_OC4# */
34 PAD_CFG_NF(GPP_I11, NONE, PLTRST, NF1),
35 /* GPP_I12 - USB_OC5# */
36 PAD_CFG_NF(GPP_I12, NONE, PLTRST, NF1),
37 /* GPP_I13 - USB_OC6# */
38 PAD_CFG_NF(GPP_I13, NONE, PLTRST, NF1),
39 /* GPP_I14 - USB_OC7# */
40 PAD_CFG_NF(GPP_I14, NONE, PLTRST, NF1),
41 /* GPP_I15 - GPIO */
42 PAD_CFG_GPI_TRIG_OWN(GPP_I15, NONE, PLTRST, OFF, ACPI),
43 /* GPP_I16 - GPIO */
44 PAD_CFG_GPI_TRIG_OWN(GPP_I16, NONE, PLTRST, OFF, ACPI),
45 /* GPP_I17 - GPIO */
46 PAD_CFG_GPI_TRIG_OWN(GPP_I17, NONE, PLTRST, OFF, ACPI),
47 /* GPP_I18 - GPIO */
48 PAD_CFG_GPI_TRIG_OWN(GPP_I18, NONE, PLTRST, OFF, ACPI),
49 /* GPP_I19 - GPIO */
50 PAD_CFG_GPI_TRIG_OWN(GPP_I19, NONE, PLTRST, OFF, ACPI),
51 /* GPP_I20 - GPIO */
52 PAD_CFG_GPI_TRIG_OWN(GPP_I20, NONE, PLTRST, OFF, ACPI),
53 /* GPP_I21 - GPIO */
54 PAD_CFG_GPI_TRIG_OWN(GPP_I21, NONE, PLTRST, OFF, ACPI),
55 /* GPP_I22 - GPIO */
56 PAD_CFG_GPI_TRIG_OWN(GPP_I22, NONE, PLTRST, OFF, ACPI),
57
58 /* ------- GPIO Group GPP_R ------- */
59
60 /* GPP_R0 - HDA_BCLK */
61 PAD_CFG_NF(GPP_R0, NONE, PLTRST, NF1),
62 /* GPP_R1 - HDA_SYNC */
63 PAD_CFG_NF(GPP_R1, NONE, PLTRST, NF1),
64 /* GPP_R2 - HDA_SDO */
65 PAD_CFG_NF(GPP_R2, NONE, PLTRST, NF1),
66 /* GPP_R3 - HDA_SDI0 */
67 PAD_CFG_NF(GPP_R3, NONE, PLTRST, NF1),
68 /* GPP_R4 - HDA_RST# */
69 PAD_CFG_NF(GPP_R4, NONE, PLTRST, NF1),
70 /* GPP_R5 - GPIO */
71 PAD_CFG_GPI_TRIG_OWN(GPP_R5, NONE, PLTRST, OFF, ACPI),
72 /* GPP_R6 - GPIO */
73 PAD_CFG_GPI_TRIG_OWN(GPP_R6, NONE, PLTRST, OFF, ACPI),
74 /* GPP_R7 - GPIO */
75 PAD_CFG_GPI_TRIG_OWN(GPP_R7, NONE, PLTRST, OFF, ACPI),
76 /* GPP_R8 - GPIO */
77 PAD_CFG_GPI_TRIG_OWN(GPP_R8, NONE, PLTRST, OFF, ACPI),
78 /* GPP_R9 - GPIO */
79 PAD_CFG_GPI_TRIG_OWN(GPP_R9, NONE, PLTRST, OFF, ACPI),
80 /* GPP_R10 - GPIO */
81 PAD_CFG_GPI_TRIG_OWN(GPP_R10, NONE, PLTRST, OFF, ACPI),
82 /* GPP_R11 - GPIO */
83 PAD_CFG_GPI_TRIG_OWN(GPP_R11, NONE, PLTRST, OFF, ACPI),
84 /* GPP_R12 - DDP3_CTRLCLK */
85 PAD_CFG_NF(GPP_R12, NONE, PLTRST, NF2),
86 /* GPP_R13 - DDP3_CTRLDATA */
87 PAD_CFG_NF(GPP_R13, NONE, PLTRST, NF2),
88 /* GPP_R14 - GPIO */
89 PAD_CFG_GPI_TRIG_OWN(GPP_R14, NONE, PLTRST, OFF, ACPI),
90 /* GPP_R15 - GPIO */
91 PAD_CFG_GPI_TRIG_OWN(GPP_R15, NONE, PLTRST, OFF, ACPI),
92 /* GPP_R16 - DDP1_CTRLCLK */
93 PAD_CFG_NF(GPP_R16, NONE, PLTRST, NF1),
94 /* GPP_R17 - DDP1_CTRLDATA */
95 PAD_CFG_NF(GPP_R17, NONE, PLTRST, NF1),
96 /* GPP_R18 - GPIO */
97 PAD_CFG_GPI_TRIG_OWN(GPP_R18, NONE, PLTRST, OFF, ACPI),
98 /* GPP_R19 - GPIO */
99 PAD_CFG_GPI_TRIG_OWN(GPP_R19, NONE, PLTRST, OFF, ACPI),
100 /* GPP_R20 - GPIO */
101 PAD_CFG_GPI_TRIG_OWN(GPP_R20, NONE, PLTRST, OFF, ACPI),
102 /* GPP_R21 - GPIO */
103 PAD_CFG_GPI_TRIG_OWN(GPP_R21, NONE, PLTRST, OFF, ACPI),
104
105 /* ------- GPIO Group GPP_J ------- */
106
107 /* GPP_J0 - GPIO */
108 PAD_CFG_GPI_TRIG_OWN(GPP_J0, NONE, PLTRST, OFF, ACPI),
109 /* GPP_J1 - GPIO */
110 PAD_CFG_GPI_TRIG_OWN(GPP_J1, NONE, PLTRST, OFF, ACPI),
111 /* GPP_J2 - CNV_BRI_DT */
112 PAD_CFG_NF(GPP_J2, NONE, PLTRST, NF1),
113 /* GPP_J3 - CNV_BRI_RSP */
114 PAD_CFG_NF(GPP_J3, NONE, PLTRST, NF1),
115 /* GPP_J4 - CNV_RGI_DT */
116 PAD_CFG_NF(GPP_J4, NONE, PLTRST, NF1),
117 /* GPP_J5 - CNV_RGI_RSP */
118 PAD_CFG_NF(GPP_J5, NONE, PLTRST, NF1),
119 /* GPP_J6 - GPIO */
120 PAD_CFG_GPI_TRIG_OWN(GPP_J6, NONE, PLTRST, OFF, ACPI),
121 /* GPP_J7 - GPIO */
122 PAD_CFG_GPI_TRIG_OWN(GPP_J7, NONE, PLTRST, OFF, ACPI),
123 /* GPP_J8 - GPIO */
124 PAD_NC(GPP_J8, NONE),
125 /* GPP_J9 - SRCCLKREQ17# */
126 PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
127 /* GPP_J10 - GPIO */
128 PAD_CFG_GPI_TRIG_OWN(GPP_J10, NONE, PLTRST, OFF, ACPI),
129 /* GPP_J11 - GPIO */
130 PAD_CFG_GPI_TRIG_OWN(GPP_J11, NONE, PLTRST, OFF, ACPI),
131
132 /* vGPIO controls certain features like CNVi, include the definitions as well */
133
134 /* ------- GPIO Group vGPIO ------- */
135 /* CNVi BT Enable, TX = 1 */
136 _PAD_CFG_STRUCT(VGPIO_0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1, 0),
137 /* CNVi BT host wake */
138 _PAD_CFG_STRUCT(VGPIO_4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
139 /* CNVi BT on USB, TX = 1 */
140 _PAD_CFG_STRUCT(VGPIO_5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1, 0),
141 _PAD_CFG_STRUCT(VGPIO_6, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
142 _PAD_CFG_STRUCT(VGPIO_7, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
143 _PAD_CFG_STRUCT(VGPIO_8, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
144 _PAD_CFG_STRUCT(VGPIO_9, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
145 _PAD_CFG_STRUCT(VGPIO_10, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* vCNV_MFUART1_TXD */
146 _PAD_CFG_STRUCT(VGPIO_11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* vCNV_MFUART1_RXD */
147 _PAD_CFG_STRUCT(VGPIO_12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* vCNV_MFUART1_CTS# */
148 _PAD_CFG_STRUCT(VGPIO_13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* vCNV_MFUART1_RTS# */
149 _PAD_CFG_STRUCT(VGPIO_18, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
150 _PAD_CFG_STRUCT(VGPIO_19, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
151 _PAD_CFG_STRUCT(VGPIO_20, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
152 _PAD_CFG_STRUCT(VGPIO_21, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
153 _PAD_CFG_STRUCT(VGPIO_22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* vISH_UART0_TXD */
154 _PAD_CFG_STRUCT(VGPIO_23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* vISH_UART0_RXD */
155 _PAD_CFG_STRUCT(VGPIO_24, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* vISH_UART0_CTS# */
156 _PAD_CFG_STRUCT(VGPIO_25, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* vISH_UART0_RTS# */
157 _PAD_CFG_STRUCT(VGPIO_30, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
158 _PAD_CFG_STRUCT(VGPIO_31, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
159 _PAD_CFG_STRUCT(VGPIO_32, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
160 _PAD_CFG_STRUCT(VGPIO_33, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
161 _PAD_CFG_STRUCT(VGPIO_34, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
162 _PAD_CFG_STRUCT(VGPIO_35, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
163 _PAD_CFG_STRUCT(VGPIO_36, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
164 _PAD_CFG_STRUCT(VGPIO_37, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
165
166 /* ------- GPIO Group vGPIO_0 ------- */
167 /* These are Virtual USB OC pins */
168 _PAD_CFG_STRUCT(VGPIO_USB_0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_0 */
169 _PAD_CFG_STRUCT(VGPIO_USB_1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_1 */
170 _PAD_CFG_STRUCT(VGPIO_USB_2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_2 */
171 _PAD_CFG_STRUCT(VGPIO_USB_3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_3 */
172 _PAD_CFG_STRUCT(VGPIO_USB_8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_8 */
173 _PAD_CFG_STRUCT(VGPIO_USB_9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_9 */
174 _PAD_CFG_STRUCT(VGPIO_USB_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_10 */
175 _PAD_CFG_STRUCT(VGPIO_USB_11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_11 */
176
177 /* ------- GPIO Community 1 ------- */
178
179 /* ------- GPIO Group GPP_B ------- */
180
181 /* GPP_B0 - GPIO */
182 PAD_CFG_GPI_TRIG_OWN(GPP_B0, NONE, PLTRST, OFF, ACPI),
183 /* GPP_B1 - GPIO */
184 PAD_CFG_GPI_TRIG_OWN(GPP_B1, NONE, PLTRST, OFF, ACPI),
185 /* GPP_B2 - GPIO */
186 PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, PLTRST, OFF, ACPI),
187 /* GPP_B3 - GPIO */
188 PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, PLTRST, OFF, ACPI),
189 /* GPP_B4 - GPIO */
190 PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, PLTRST, OFF, ACPI),
191 /* GPP_B5 - GPIO */
192 PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, PLTRST, OFF, ACPI),
193 /* GPP_B6 - GPIO */
194 PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, ACPI),
195 /* GPP_B7 - GPIO */
196 PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, PLTRST, OFF, ACPI),
197 /* GPP_B8 - GPIO */
198 PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI),
199 /* GPP_B9 - GPIO */
200 PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, PLTRST, OFF, ACPI),
201 /* GPP_B10 - GPIO */
202 PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, PLTRST, OFF, ACPI),
203 /* GPP_B11 - GPIO */
204 PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI),
205 /* GPP_B12 - SLP_S0# */
206 PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1),
207 /* GPP_B13 - PLTRST# */
208 PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1),
209 /* GPP_B14 - SPKR */
210 PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1),
211 /* GPP_B15 - GPIO */
212 PAD_CFG_GPO(GPP_B15, 0, PLTRST),
213 /* GPP_B16 - GPIO */
214 PAD_CFG_GPO(GPP_B16, 0, PLTRST),
215 /* GPP_B17 - GPIO */
216 PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, PLTRST, OFF, ACPI),
217 /* GPP_B18 - PMCALERT# */
218 PAD_CFG_NF(GPP_B18, NONE, PLTRST, NF1),
219 /* GPP_B19 - GPIO */
220 PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, PLTRST, OFF, ACPI),
221 /* GPP_B20 - GPIO */
222 PAD_CFG_GPI_TRIG_OWN(GPP_B20, NONE, PLTRST, OFF, ACPI),
223 /* GPP_B21 - GPIO */
224 PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, PLTRST, OFF, ACPI),
225 /* GPP_B22 - GPIO */
226 PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, PLTRST, OFF, ACPI),
227 /* GPP_B23 - GPIO */
228 PAD_CFG_GPI_TRIG_OWN(GPP_B23, NONE, PLTRST, OFF, ACPI),
229
230 /* ------- GPIO Group GPP_G ------- */
231
232 /* GPP_G0 - GPIO */
233 PAD_CFG_GPO(GPP_G0, 0, PLTRST),
234 /* GPP_G1 - GPIO */
235 PAD_CFG_GPO(GPP_G1, 1, RSMRST),
236 /* GPP_G2 - DNX_FORCE_RELOAD */
237 PAD_CFG_NF(GPP_G2, NONE, PLTRST, NF1),
238 /* GPP_G3 - GPIO */
239 PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI),
240 /* GPP_G4 - GPIO */
241 PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI),
242 /* GPP_G5 - SLP_DRAM# */
243 PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1),
244 /* GPP_G6 - GPIO */
245 PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI),
246 /* GPP_G7 - GPIO */
247 PAD_NC(GPP_G7, NONE),
248
249 /* ------- GPIO Group GPP_H ------- */
250
251 /* GPP_H0 - GPIO */
252 PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, PLTRST, OFF, ACPI),
253 /* GPP_H1 - GPIO */
254 PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI),
255 /* GPP_H2 - SRCCLKREQ8# */
256 PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
257 /* GPP_H3 - SRCCLKREQ9# */
258 PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
259 /* GPP_H4 - SRCCLKREQ10# */
260 PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
261 /* GPP_H5 - GPIO */
262 PAD_NC(GPP_H5, NONE),
263 /* GPP_H6 - SRCCLKREQ12# */
264 PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
265 /* GPP_H7 - SRCCLKREQ13# */
266 PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
267 /* GPP_H8 - SRCCLKREQ14# */
268 PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
269 /* GPP_H9 - SRCCLKREQ15# */
270 PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
271 /* GPP_H10 - GPIO */
272 PAD_CFG_GPI_TRIG_OWN(GPP_H10, NONE, PLTRST, OFF, ACPI),
273 /* GPP_H11 - GPIO */
274 PAD_CFG_GPI_TRIG_OWN(GPP_H11, NONE, PLTRST, OFF, ACPI),
275 /* GPP_H12 - GPIO */
276 PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, PLTRST, OFF, ACPI),
277 /* GPP_H13 - GPIO */
278 PAD_CFG_GPI_TRIG_OWN(GPP_H13, NONE, PLTRST, OFF, ACPI),
279 /* GPP_H14 - GPIO */
280 PAD_CFG_GPI_TRIG_OWN(GPP_H14, NONE, PLTRST, OFF, ACPI),
281 /* GPP_H15 - GPIO */
282 PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, ACPI),
283 /* GPP_H16 - GPIO */
284 PAD_CFG_GPI_TRIG_OWN(GPP_H16, NONE, PLTRST, OFF, ACPI),
285 /* GPP_H17 - GPIO */
286 PAD_CFG_GPI_TRIG_OWN(GPP_H17, NONE, PLTRST, OFF, ACPI),
287 /* GPP_H18 - GPIO */
288 PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, PLTRST, OFF, ACPI),
289 /* GPP_H19 - GPIO */
290 PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, ACPI),
291 /* GPP_H20 - GPIO */
292 PAD_CFG_GPO(GPP_H20, 1, PLTRST),
293 /* GPP_H21 - GPIO */
294 PAD_CFG_GPO(GPP_H21, 0, PLTRST),
295 /* GPP_H22 - GPIO */
296 PAD_CFG_GPO(GPP_H22, 1, PLTRST),
297 /* GPP_H23 - GPIO */
298 PAD_CFG_GPO(GPP_H23, 1, PLTRST),
299
300 /* ------- GPIO Community 2 ------- */
301
302 /* ------- GPIO Group GPD ------- */
303
304 /* GPD0 - GPIO */
305 PAD_CFG_GPI_TRIG_OWN(GPD0, NONE, PLTRST, OFF, ACPI),
306 /* GPD1 - GPIO */
307 PAD_CFG_GPI_TRIG_OWN(GPD1, NONE, PLTRST, OFF, ACPI),
308 /* GPD2 - LAN_WAKE# */
309 PAD_CFG_NF(GPD2, NONE, PLTRST, NF1),
310 /* GPD3 - PWRBTN# */
311 PAD_CFG_NF(GPD3, NONE, PLTRST, NF1),
312 /* GPD4 - SLP_S3# */
313 PAD_CFG_NF(GPD4, NONE, PLTRST, NF1),
314 /* GPD5 - SLP_S4# */
315 PAD_CFG_NF(GPD5, NONE, PLTRST, NF1),
316 /* GPD6 - SLP_A# */
317 PAD_CFG_NF(GPD6, NONE, PLTRST, NF1),
318 /* GPD7 - GPIO */
319 PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, PLTRST, OFF, ACPI),
320 /* GPD8 - SUSCLK */
321 PAD_CFG_NF(GPD8, NONE, PLTRST, NF1),
322 /* GPD9 - SLP_WLAN# */
323 PAD_CFG_NF(GPD9, NONE, PLTRST, NF1),
324 /* GPD10 - SLP_S5# */
325 PAD_CFG_NF(GPD10, NONE, PLTRST, NF1),
326 /* GPD11 - GPIO */
327 PAD_CFG_GPI_TRIG_OWN(GPD11, NONE, PLTRST, OFF, ACPI),
328 /* GPD12 - GPIO */
329 PAD_CFG_TERM_GPO(GPD12, 1, DN_5K, RSMRST),
330
331 /* ------- GPIO Community 3 ------- */
332
333 /* ------- GPIO Group GPP_A ------- */
334
335 /* GPP_A0 - ESPI_IO0 */
336 PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1),
337 /* GPP_A1 - ESPI_IO1 */
338 PAD_CFG_NF(GPP_A1, NONE, PLTRST, NF1),
339 /* GPP_A2 - ESPI_IO2 */
340 PAD_CFG_NF(GPP_A2, NONE, PLTRST, NF1),
341 /* GPP_A3 - ESPI_IO3 */
342 PAD_CFG_NF(GPP_A3, NONE, PLTRST, NF1),
343 /* GPP_A4 - ESPI_CS0# */
344 PAD_CFG_NF(GPP_A4, NONE, PLTRST, NF1),
345 /* GPP_A5 - ESPI_CLK */
346 PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1),
347 /* GPP_A6 - ESPI_RESET# */
348 PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1),
349 /* GPP_A7 - GPIO */
350 PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI),
351 /* GPP_A8 - GPIO */
352 PAD_CFG_GPI_TRIG_OWN(GPP_A8, NONE, PLTRST, OFF, ACPI),
353 /* GPP_A9 - GPIO */
354 PAD_CFG_GPI_TRIG_OWN(GPP_A9, NONE, PLTRST, OFF, ACPI),
355 /* GPP_A10 - GPIO */
356 PAD_CFG_GPI_TRIG_OWN(GPP_A10, NONE, PLTRST, OFF, ACPI),
357 /* GPP_A11 - GPIO */
358 PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, PLTRST, OFF, ACPI),
359 /* GPP_A12 - GPIO */
360 PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, PLTRST, OFF, ACPI),
361 /* GPP_A13 - GPIO */
362 PAD_CFG_GPI_TRIG_OWN(GPP_A13, NONE, PLTRST, OFF, ACPI),
363 /* GPP_A14 - GPIO */
364 PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, PLTRST, OFF, ACPI),
365
366 /* ------- GPIO Group GPP_C ------- */
367
368 /* GPP_C0 - SMBCLK */
369 PAD_CFG_NF(GPP_C0, NONE, PLTRST, NF1),
370 /* GPP_C1 - SMBDATA */
371 PAD_CFG_NF(GPP_C1, NONE, PLTRST, NF1),
372 /* GPP_C2 - SMBALERT# */
373 PAD_CFG_NF(GPP_C2, NONE, PLTRST, NF1),
374 /* GPP_C3 - GPIO */
375 PAD_CFG_GPO(GPP_C3, 1, PLTRST),
376 /* GPP_C4 - GPIO */
377 PAD_CFG_GPO(GPP_C4, 1, PLTRST),
378 /* GPP_C5 - GPIO */
379 PAD_CFG_GPI_TRIG_OWN(GPP_C5, NONE, PLTRST, OFF, ACPI),
380 /* GPP_C6 - GPIO */
381 PAD_CFG_GPO(GPP_C6, 0, PLTRST),
382 /* GPP_C7 - GPIO */
383 PAD_CFG_GPO(GPP_C7, 0, PLTRST),
384 /* GPP_C8 - GPIO */
385 PAD_CFG_GPO(GPP_C8, 1, RSMRST),
386 /* GPP_C9 - GPIO */
387 PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI),
388 /* GPP_C10 - GPIO */
389 PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, PLTRST, OFF, ACPI),
390 /* GPP_C11 - GPIO */
391 PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, PLTRST, OFF, ACPI),
392 /* GPP_C12 - GPIO */
393 PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, PLTRST, OFF, ACPI),
394 /* GPP_C13 - GPIO */
395 PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, PLTRST, OFF, ACPI),
396 /* GPP_C14 - GPIO */
397 PAD_CFG_GPI_TRIG_OWN(GPP_C14, NONE, PLTRST, OFF, ACPI),
398 /* GPP_C15 - GPIO */
399 PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, PLTRST, OFF, ACPI),
400 /* GPP_C16 - I2C0_SDA */
401 PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
402 /* GPP_C17 - I2C0_SCL */
403 PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
404 /* GPP_C18 - GPIO */
405 PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, PLTRST, OFF, ACPI),
406 /* GPP_C19 - GPIO */
407 PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, PLTRST, OFF, ACPI),
408 /* GPP_C20 - GPIO */
409 PAD_CFG_GPO(GPP_C20, 0, PLTRST),
410 /* GPP_C21 - GPIO */
411 PAD_CFG_GPO(GPP_C21, 0, PLTRST),
412 /* GPP_C22 - GPIO */
413 PAD_CFG_GPI_TRIG_OWN(GPP_C22, NONE, PLTRST, OFF, ACPI),
414 /* GPP_C23 - GPIO */
415 PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, PLTRST, OFF, ACPI),
416
417 /* CPU PCIe CLKREQ virtual wire message buses */
418 _PAD_CFG_STRUCT(VGPIO_PCIE_0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
419 _PAD_CFG_STRUCT(VGPIO_PCIE_1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
420 _PAD_CFG_STRUCT(VGPIO_PCIE_2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
421 _PAD_CFG_STRUCT(VGPIO_PCIE_3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
422 _PAD_CFG_STRUCT(VGPIO_PCIE_4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
423 _PAD_CFG_STRUCT(VGPIO_PCIE_5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
424 _PAD_CFG_STRUCT(VGPIO_PCIE_6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
425 _PAD_CFG_STRUCT(VGPIO_PCIE_7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
426 _PAD_CFG_STRUCT(VGPIO_PCIE_8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
427 _PAD_CFG_STRUCT(VGPIO_PCIE_9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
428 _PAD_CFG_STRUCT(VGPIO_PCIE_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
429 _PAD_CFG_STRUCT(VGPIO_PCIE_11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
430 _PAD_CFG_STRUCT(VGPIO_PCIE_12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
431 _PAD_CFG_STRUCT(VGPIO_PCIE_13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
432 _PAD_CFG_STRUCT(VGPIO_PCIE_14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
433 _PAD_CFG_STRUCT(VGPIO_PCIE_15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
434 _PAD_CFG_STRUCT(VGPIO_PCIE_64, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
435 _PAD_CFG_STRUCT(VGPIO_PCIE_65, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
436 _PAD_CFG_STRUCT(VGPIO_PCIE_66, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
437 _PAD_CFG_STRUCT(VGPIO_PCIE_67, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
438
439 _PAD_CFG_STRUCT(VGPIO_PCIE_16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
440 _PAD_CFG_STRUCT(VGPIO_PCIE_17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
441 _PAD_CFG_STRUCT(VGPIO_PCIE_18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
442 _PAD_CFG_STRUCT(VGPIO_PCIE_19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
443 _PAD_CFG_STRUCT(VGPIO_PCIE_20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
444 _PAD_CFG_STRUCT(VGPIO_PCIE_21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
445 _PAD_CFG_STRUCT(VGPIO_PCIE_22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
446 _PAD_CFG_STRUCT(VGPIO_PCIE_23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
447 _PAD_CFG_STRUCT(VGPIO_PCIE_24, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
448 _PAD_CFG_STRUCT(VGPIO_PCIE_25, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
449 _PAD_CFG_STRUCT(VGPIO_PCIE_26, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
450 _PAD_CFG_STRUCT(VGPIO_PCIE_27, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
451 _PAD_CFG_STRUCT(VGPIO_PCIE_28, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
452 _PAD_CFG_STRUCT(VGPIO_PCIE_29, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
453 _PAD_CFG_STRUCT(VGPIO_PCIE_30, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
454 _PAD_CFG_STRUCT(VGPIO_PCIE_31, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
455 _PAD_CFG_STRUCT(VGPIO_PCIE_68, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
456 _PAD_CFG_STRUCT(VGPIO_PCIE_69, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
457 _PAD_CFG_STRUCT(VGPIO_PCIE_70, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
458 _PAD_CFG_STRUCT(VGPIO_PCIE_71, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
459
460 _PAD_CFG_STRUCT(VGPIO_PCIE_32, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
461 _PAD_CFG_STRUCT(VGPIO_PCIE_33, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
462 _PAD_CFG_STRUCT(VGPIO_PCIE_34, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
463 _PAD_CFG_STRUCT(VGPIO_PCIE_35, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
464 _PAD_CFG_STRUCT(VGPIO_PCIE_36, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
465 _PAD_CFG_STRUCT(VGPIO_PCIE_37, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
466 _PAD_CFG_STRUCT(VGPIO_PCIE_38, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
467 _PAD_CFG_STRUCT(VGPIO_PCIE_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
468 _PAD_CFG_STRUCT(VGPIO_PCIE_40, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
469 _PAD_CFG_STRUCT(VGPIO_PCIE_41, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
470 _PAD_CFG_STRUCT(VGPIO_PCIE_42, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
471 _PAD_CFG_STRUCT(VGPIO_PCIE_43, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
472 _PAD_CFG_STRUCT(VGPIO_PCIE_44, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
473 _PAD_CFG_STRUCT(VGPIO_PCIE_45, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
474 _PAD_CFG_STRUCT(VGPIO_PCIE_46, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
475 _PAD_CFG_STRUCT(VGPIO_PCIE_47, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
476 _PAD_CFG_STRUCT(VGPIO_PCIE_72, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
477 _PAD_CFG_STRUCT(VGPIO_PCIE_73, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
478 _PAD_CFG_STRUCT(VGPIO_PCIE_74, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
479 _PAD_CFG_STRUCT(VGPIO_PCIE_75, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
480
481 _PAD_CFG_STRUCT(VGPIO_PCIE_48, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
482 _PAD_CFG_STRUCT(VGPIO_PCIE_49, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
483 _PAD_CFG_STRUCT(VGPIO_PCIE_50, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
484 _PAD_CFG_STRUCT(VGPIO_PCIE_51, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
485 _PAD_CFG_STRUCT(VGPIO_PCIE_52, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
486 _PAD_CFG_STRUCT(VGPIO_PCIE_53, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
487 _PAD_CFG_STRUCT(VGPIO_PCIE_54, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
488 _PAD_CFG_STRUCT(VGPIO_PCIE_55, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
489 _PAD_CFG_STRUCT(VGPIO_PCIE_56, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
490 _PAD_CFG_STRUCT(VGPIO_PCIE_57, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
491 _PAD_CFG_STRUCT(VGPIO_PCIE_58, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
492 _PAD_CFG_STRUCT(VGPIO_PCIE_59, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
493 _PAD_CFG_STRUCT(VGPIO_PCIE_60, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
494 _PAD_CFG_STRUCT(VGPIO_PCIE_61, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
495 _PAD_CFG_STRUCT(VGPIO_PCIE_62, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
496 _PAD_CFG_STRUCT(VGPIO_PCIE_63, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
497 _PAD_CFG_STRUCT(VGPIO_PCIE_76, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
498 _PAD_CFG_STRUCT(VGPIO_PCIE_77, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
499 _PAD_CFG_STRUCT(VGPIO_PCIE_78, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
500 _PAD_CFG_STRUCT(VGPIO_PCIE_79, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
501
502 /* ------- GPIO Community 4 ------- */
503
504 /* ------- GPIO Group GPP_S ------- */
505
506 /* GPP_S0 - GPIO */
507 PAD_CFG_GPI_TRIG_OWN(GPP_S0, NONE, PLTRST, OFF, ACPI),
508 /* GPP_S1 - GPIO */
509 PAD_CFG_GPI_TRIG_OWN(GPP_S1, NONE, PLTRST, OFF, ACPI),
510 /* GPP_S2 - GPIO */
511 PAD_CFG_GPI_TRIG_OWN(GPP_S2, NONE, PLTRST, OFF, ACPI),
512 /* GPP_S3 - GPIO */
513 PAD_CFG_GPI_TRIG_OWN(GPP_S3, NONE, PLTRST, OFF, ACPI),
514 /* GPP_S4 - GPIO */
515 PAD_CFG_GPI_TRIG_OWN(GPP_S4, NONE, PLTRST, OFF, ACPI),
516 /* GPP_S5 - GPIO */
517 PAD_CFG_GPI_TRIG_OWN(GPP_S5, NONE, PLTRST, OFF, ACPI),
518 /* GPP_S6 - GPIO */
519 PAD_CFG_GPI_TRIG_OWN(GPP_S6, NONE, PLTRST, OFF, ACPI),
520 /* GPP_S7 - GPIO */
521 PAD_CFG_GPI_TRIG_OWN(GPP_S7, NONE, PLTRST, OFF, ACPI),
522
523 /* ------- GPIO Group GPP_E ------- */
524
525 /* GPP_E0 - SATAXPCIE0 */
526 PAD_CFG_NF(GPP_E0, NONE, PLTRST, NF1),
527 /* GPP_E1 - SATAXPCIE1 */
528 PAD_CFG_NF(GPP_E1, NONE, PLTRST, NF1),
529 /* GPP_E2 - GPIO */
530 PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, PLTRST, OFF, ACPI),
531 /* GPP_E3 - GPIO */
532 PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, PLTRST, OFF, ACPI),
533 /* GPP_E4 - GPIO */
534 PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, PLTRST, OFF, ACPI),
535 /* GPP_E5 - GPIO */
536 PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, PLTRST, OFF, ACPI),
537 /* GPP_E6 - GPIO */
538 PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, PLTRST, OFF, ACPI),
539 /* GPP_E7 - TPM_PIRQ# */
540 PAD_CFG_GPI_APIC_LOW(GPP_E7, NONE, PLTRST),
541 /* GPP_E8 - SATALED# */
542 PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1),
543 /* GPP_E9 - USB_OC0# */
544 PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF1),
545 /* GPP_E10 - USB_OC1# */
546 PAD_CFG_NF(GPP_E10, NONE, PLTRST, NF1),
547 /* GPP_E11 - USB_OC2# */
548 PAD_CFG_NF(GPP_E11, NONE, PLTRST, NF1),
549 /* GPP_E12 - USB_OC3# */
550 PAD_CFG_NF(GPP_E12, NONE, PLTRST, NF1),
551 /* GPP_E13 - GPIO */
552 PAD_CFG_GPI_TRIG_OWN(GPP_E13, NONE, PLTRST, OFF, ACPI),
553 /* GPP_E14 - GPIO */
554 PAD_CFG_GPI_TRIG_OWN(GPP_E14, NONE, PLTRST, OFF, ACPI),
555 /* GPP_E15 - GPIO */
556 PAD_CFG_GPI_TRIG_OWN(GPP_E15, NONE, PLTRST, OFF, ACPI),
557 /* GPP_E16 - GPIO */
558 PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI),
559 /* GPP_E17 - GPIO */
560 PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, PLTRST, OFF, ACPI),
561 /* GPP_E18 - GPIO */
562 PAD_CFG_GPI_TRIG_OWN(GPP_E18, NONE, PLTRST, OFF, ACPI),
563 /* GPP_E19 - GPIO */
564 PAD_CFG_GPI_TRIG_OWN(GPP_E19, NONE, PLTRST, OFF, ACPI),
565 /* GPP_E20 - GPIO */
566 PAD_CFG_GPI_TRIG_OWN(GPP_E20, NONE, PLTRST, OFF, ACPI),
567 /* GPP_E21 - GPIO */
568 PAD_CFG_GPI_TRIG_OWN(GPP_E21, NONE, PLTRST, OFF, ACPI),
569
570 /* ------- GPIO Group GPP_K ------- */
571
572 /* GPP_K0 - GPIO */
573 PAD_CFG_GPI_TRIG_OWN(GPP_K0, NONE, PLTRST, OFF, ACPI),
574 /* GPP_K1 - GPIO */
575 PAD_CFG_GPI_TRIG_OWN(GPP_K1, NONE, PLTRST, OFF, ACPI),
576 /* GPP_K2 - GPIO */
577 PAD_CFG_GPI_TRIG_OWN(GPP_K2, NONE, PLTRST, OFF, ACPI),
578 /* GPP_K3 - GPIO */
579 PAD_CFG_GPI_TRIG_OWN(GPP_K3, NONE, PLTRST, OFF, ACPI),
580 /* GPP_K4 - GPIO */
581 PAD_CFG_GPI_TRIG_OWN(GPP_K4, NONE, PLTRST, OFF, ACPI),
582 /* GPP_K5 - GPIO */
583 PAD_CFG_GPI_TRIG_OWN(GPP_K5, NONE, PLTRST, OFF, ACPI),
584 /* GPP_K6 - n/a */
585 PAD_CFG_NF(GPP_K6, UP_20K, DEEP, NF2),
586 /* GPP_K7 - n/a */
587 PAD_CFG_NF(GPP_K7, DN_20K, DEEP, NF2),
588 /* GPP_K8 - CORE_VID0 */
589 PAD_CFG_NF(GPP_K8, NONE, PLTRST, NF1),
590 /* GPP_K9 - CORE_VID1 */
591 PAD_CFG_NF(GPP_K9, NONE, PLTRST, NF1),
592 /* GPP_K10 - n/a */
593 PAD_CFG_NF(GPP_K10, UP_20K, DEEP, NF2),
594 /* GPP_K11 - GPIO */
595 PAD_CFG_GPI_TRIG_OWN(GPP_K11, NONE, PLTRST, OFF, ACPI),
596
597 /* ------- GPIO Group GPP_F ------- */
598
599 /* GPP_F0 - GPIO */
600 PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, PLTRST, OFF, ACPI),
601 /* GPP_F1 - GPIO */
602 PAD_CFG_GPI_SCI(GPP_F1, NONE, PLTRST, EDGE_SINGLE, INVERT),
603 /* GPP_F2 - GPIO */
604 PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, PLTRST, OFF, ACPI),
605 /* GPP_F3 - GPIO */
606 PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI),
607 /* GPP_F4 - GPIO */
608 PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, PLTRST, OFF, ACPI),
609 /* GPP_F5 - GPIO */
610 PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI),
611 /* GPP_F6 - GPIO */
612 PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, PLTRST, OFF, ACPI),
613 /* GPP_F7 - GPIO */
614 PAD_CFG_GPI_TRIG_OWN(GPP_F7, NONE, PLTRST, OFF, ACPI),
615 /* GPP_F8 - SATA_DEVSLP6 */
616 PAD_CFG_NF(GPP_F8, NONE, PLTRST, NF1),
617 /* GPP_F9 - SATA_DEVSLP7 */
618 PAD_CFG_NF(GPP_F9, NONE, PLTRST, NF1),
619 /* GPP_F10 - GPIO */
620 PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, PLTRST, OFF, ACPI),
621 /* GPP_F11 - GPIO */
622 PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI),
623 /* GPP_F12 - GPIO */
624 PAD_CFG_GPO(GPP_F12, 1, RSMRST),
625 /* GPP_F13 - GPIO */
626 PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, PLTRST, OFF, ACPI),
627 /* GPP_F14 - PS_ON# */
628 PAD_CFG_NF(GPP_F14, NONE, PLTRST, NF1),
629 /* GPP_F15 - GPIO */
630 PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, PLTRST, OFF, ACPI),
631 /* GPP_F16 - GPIO */
632 PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, PLTRST, OFF, ACPI),
633 /* GPP_F17 - GPIO */
634 PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI),
635 /* GPP_F18 - GPIO */
636 PAD_CFG_GPI_TRIG_OWN(GPP_F18, NONE, PLTRST, OFF, ACPI),
637 /* GPP_F19 - GPIO */
638 PAD_CFG_GPI_TRIG_OWN(GPP_F19, NONE, PLTRST, OFF, ACPI),
639 /* GPP_F20 - GPIO */
640 PAD_CFG_GPI_TRIG_OWN(GPP_F20, NONE, PLTRST, OFF, ACPI),
641 /* GPP_F21 - GPIO */
642 PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, PLTRST, OFF, ACPI),
643 /* GPP_F22 - GPIO */
644 PAD_CFG_GPI_TRIG_OWN(GPP_F22, NONE, PLTRST, OFF, ACPI),
645 /* GPP_F23 - GPIO */
646 PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, PLTRST, OFF, ACPI),
647
648 /* ------- GPIO Community 5 ------- */
649
650 /* ------- GPIO Group GPP_D ------- */
651
652 /* GPP_D0 - SRCCLKREQ0# */
653 PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
654 /* GPP_D1 - GPIO */
655 PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI),
656 /* GPP_D2 - GPIO */
657 PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, ACPI),
658 /* GPP_D3 - GPIO */
659 PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI),
660 /* GPP_D4 - SML1CLK */
661 PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1),
662 /* GPP_D5 - CNV_RF_RESET# */
663 PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF2),
664 /* GPP_D6 - MODEM_CLKREQ */
665 PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF3),
666 /* GPP_D7 - GPIO */
667 PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, PLTRST, OFF, ACPI),
668 /* GPP_D8 - GPIO */
669 PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, PLTRST, OFF, ACPI),
670 /* GPP_D9 - SML0CLK */
671 PAD_CFG_NF(GPP_D9, NONE, PLTRST, NF1),
672 /* GPP_D10 - SML0DATA */
673 PAD_CFG_NF(GPP_D10, NONE, PLTRST, NF1),
674 /* GPP_D11 - GPIO */
675 PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, PLTRST, OFF, ACPI),
676 /* GPP_D12 - GPIO */
677 PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, PLTRST, OFF, ACPI),
678 /* GPP_D13 - GPIO */
679 PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, PLTRST, OFF, ACPI),
680 /* GPP_D14 - GPIO */
681 PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, OFF, ACPI),
682 /* GPP_D15 - SML1DATA */
683 PAD_CFG_NF(GPP_D15, NONE, PLTRST, NF1),
684 /* GPP_D16 - GPIO */
685 PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, PLTRST, OFF, ACPI),
686 /* GPP_D17 - GPIO */
687 PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, PLTRST, OFF, ACPI),
688 /* GPP_D18 - GPIO */
689 PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, PLTRST, OFF, ACPI),
690 /* GPP_D19 - GPIO */
691 PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, PLTRST, OFF, ACPI),
692 /* GPP_D20 - GPIO */
693 PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, PLTRST, OFF, ACPI),
694 /* GPP_D21 - GPIO */
695 PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, PLTRST, OFF, ACPI),
696 /* GPP_D22 - GPIO */
697 PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PLTRST, OFF, ACPI),
698 /* GPP_D23 - GPIO */
699 PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, PLTRST, OFF, ACPI),
700 };
701
702 /* PCIe CLK REQs as per devicetree.cb */
703 static const struct pad_config clkreq_disabled_table[] = {
704 /* GPP_J9 - SRCCLKREQ17# */
705 PAD_NC(GPP_J9, NONE),
706 /* GPP_H2 - SRCCLKREQ8# */
707 PAD_NC(GPP_H2, NONE),
708 /* GPP_H3 - SRCCLKREQ9# */
709 PAD_NC(GPP_H3, NONE),
710 /* GPP_H4 - SRCCLKREQ10# */
711 PAD_NC(GPP_H4, NONE),
712 /* GPP_H6 - SRCCLKREQ12# */
713 PAD_NC(GPP_H6, NONE),
714 /* GPP_H7 - SRCCLKREQ13# */
715 PAD_NC(GPP_H7, NONE),
716 /* GPP_H8 - SRCCLKREQ14# */
717 PAD_NC(GPP_H8, NONE),
718 /* GPP_H9 - SRCCLKREQ15# */
719 PAD_NC(GPP_H9, NONE),
720 /* GPP_D0 - SRCCLKREQ0# */
721 PAD_NC(GPP_D0, NONE),
722
723 /* CPU PCIe CLKREQ virtual wire message buses */
724 _PAD_CFG_STRUCT(VGPIO_PCIE_0, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
725 _PAD_CFG_STRUCT(VGPIO_PCIE_1, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
726 _PAD_CFG_STRUCT(VGPIO_PCIE_2, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
727 _PAD_CFG_STRUCT(VGPIO_PCIE_3, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
728 _PAD_CFG_STRUCT(VGPIO_PCIE_4, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
729 _PAD_CFG_STRUCT(VGPIO_PCIE_5, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
730 _PAD_CFG_STRUCT(VGPIO_PCIE_6, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
731 _PAD_CFG_STRUCT(VGPIO_PCIE_7, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
732 _PAD_CFG_STRUCT(VGPIO_PCIE_8, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
733 _PAD_CFG_STRUCT(VGPIO_PCIE_9, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
734 _PAD_CFG_STRUCT(VGPIO_PCIE_10, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
735 _PAD_CFG_STRUCT(VGPIO_PCIE_11, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
736 _PAD_CFG_STRUCT(VGPIO_PCIE_12, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
737 _PAD_CFG_STRUCT(VGPIO_PCIE_13, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
738 _PAD_CFG_STRUCT(VGPIO_PCIE_14, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
739 _PAD_CFG_STRUCT(VGPIO_PCIE_15, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
740 _PAD_CFG_STRUCT(VGPIO_PCIE_64, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
741 _PAD_CFG_STRUCT(VGPIO_PCIE_65, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
742 _PAD_CFG_STRUCT(VGPIO_PCIE_66, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
743 _PAD_CFG_STRUCT(VGPIO_PCIE_67, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
744
745 _PAD_CFG_STRUCT(VGPIO_PCIE_16, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
746 _PAD_CFG_STRUCT(VGPIO_PCIE_17, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
747 _PAD_CFG_STRUCT(VGPIO_PCIE_18, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
748 _PAD_CFG_STRUCT(VGPIO_PCIE_19, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
749 _PAD_CFG_STRUCT(VGPIO_PCIE_20, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
750 _PAD_CFG_STRUCT(VGPIO_PCIE_21, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
751 _PAD_CFG_STRUCT(VGPIO_PCIE_22, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
752 _PAD_CFG_STRUCT(VGPIO_PCIE_23, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
753 _PAD_CFG_STRUCT(VGPIO_PCIE_24, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
754 _PAD_CFG_STRUCT(VGPIO_PCIE_25, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
755 _PAD_CFG_STRUCT(VGPIO_PCIE_26, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
756 _PAD_CFG_STRUCT(VGPIO_PCIE_27, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
757 _PAD_CFG_STRUCT(VGPIO_PCIE_28, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
758 _PAD_CFG_STRUCT(VGPIO_PCIE_29, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
759 _PAD_CFG_STRUCT(VGPIO_PCIE_30, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
760 _PAD_CFG_STRUCT(VGPIO_PCIE_31, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
761 _PAD_CFG_STRUCT(VGPIO_PCIE_68, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
762 _PAD_CFG_STRUCT(VGPIO_PCIE_69, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
763 _PAD_CFG_STRUCT(VGPIO_PCIE_70, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
764 _PAD_CFG_STRUCT(VGPIO_PCIE_71, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
765
766 _PAD_CFG_STRUCT(VGPIO_PCIE_32, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
767 _PAD_CFG_STRUCT(VGPIO_PCIE_33, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
768 _PAD_CFG_STRUCT(VGPIO_PCIE_34, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
769 _PAD_CFG_STRUCT(VGPIO_PCIE_35, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
770 _PAD_CFG_STRUCT(VGPIO_PCIE_36, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
771 _PAD_CFG_STRUCT(VGPIO_PCIE_37, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
772 _PAD_CFG_STRUCT(VGPIO_PCIE_38, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
773 _PAD_CFG_STRUCT(VGPIO_PCIE_39, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
774 _PAD_CFG_STRUCT(VGPIO_PCIE_40, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
775 _PAD_CFG_STRUCT(VGPIO_PCIE_41, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
776 _PAD_CFG_STRUCT(VGPIO_PCIE_42, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
777 _PAD_CFG_STRUCT(VGPIO_PCIE_43, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
778 _PAD_CFG_STRUCT(VGPIO_PCIE_44, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
779 _PAD_CFG_STRUCT(VGPIO_PCIE_45, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
780 _PAD_CFG_STRUCT(VGPIO_PCIE_46, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
781 _PAD_CFG_STRUCT(VGPIO_PCIE_47, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
782 _PAD_CFG_STRUCT(VGPIO_PCIE_72, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
783 _PAD_CFG_STRUCT(VGPIO_PCIE_73, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
784 _PAD_CFG_STRUCT(VGPIO_PCIE_74, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
785 _PAD_CFG_STRUCT(VGPIO_PCIE_75, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
786
787 _PAD_CFG_STRUCT(VGPIO_PCIE_48, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
788 _PAD_CFG_STRUCT(VGPIO_PCIE_49, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
789 _PAD_CFG_STRUCT(VGPIO_PCIE_50, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
790 _PAD_CFG_STRUCT(VGPIO_PCIE_51, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
791 _PAD_CFG_STRUCT(VGPIO_PCIE_52, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
792 _PAD_CFG_STRUCT(VGPIO_PCIE_53, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
793 _PAD_CFG_STRUCT(VGPIO_PCIE_54, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
794 _PAD_CFG_STRUCT(VGPIO_PCIE_55, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
795 _PAD_CFG_STRUCT(VGPIO_PCIE_56, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
796 _PAD_CFG_STRUCT(VGPIO_PCIE_57, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
797 _PAD_CFG_STRUCT(VGPIO_PCIE_58, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
798 _PAD_CFG_STRUCT(VGPIO_PCIE_59, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
799 _PAD_CFG_STRUCT(VGPIO_PCIE_60, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
800 _PAD_CFG_STRUCT(VGPIO_PCIE_61, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
801 _PAD_CFG_STRUCT(VGPIO_PCIE_62, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
802 _PAD_CFG_STRUCT(VGPIO_PCIE_63, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
803 _PAD_CFG_STRUCT(VGPIO_PCIE_76, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
804 _PAD_CFG_STRUCT(VGPIO_PCIE_77, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
805 _PAD_CFG_STRUCT(VGPIO_PCIE_78, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
806 _PAD_CFG_STRUCT(VGPIO_PCIE_79, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
807 };
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