src/mainboard/prodrive/atlas/devicetree.cb

   1 chip soc/intel/alderlake
   2
   3         # GPE configuration
   4         # Note that GPE events called out in ASL code rely on this
   5         # route. i.e. If this route changes then the affected GPE
   6         # offset bits also need to be changed.
   7         register "pmc_gpe0_dw0" = "GPP_B"
   8         register "pmc_gpe0_dw1" = "GPP_D"
   9         register "pmc_gpe0_dw2" = "GPP_E"
  10
  11         # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
  12         register "gen1_dec" = "0x00fc0801"
  13         register "gen2_dec" = "0x000c0201"
  14         # EC memory map range is 0x900-0x9ff
  15         register "gen3_dec" = "0x00fc0901"
  16         # EC EMI 0 range is 0xc00 - 0xc0f
  17         register "gen4_dec" = "0x000c0c01"
  18
  19         # SaGv Configuration
  20         register "sagv" = "CONFIG(ATLAS_ENABLE_SAGV) ? SaGv_Enabled : SaGv_Disabled"
  21
  22         # Disable S0ix
  23         register "s0ix_enable" = "false"
  24
  25         # Display configuration (4 DPs)
  26         register "ddi_ports_config" = "{
  27                 [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
  28                 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
  29                 [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
  30                 [DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
  31         }"
  32
  33         # Acoustic settings
  34         register "acoustic_noise_mitigation" = "true"
  35         register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_4"
  36         register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_4"
  37         register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
  38         register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
  39
  40         # USB configuration
  41         register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
  42         register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
  43         register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"
  44         register "usb2_ports[3]" = "USB2_PORT_MID(OC1)"
  45         register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
  46         register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
  47         register "usb2_ports[6]" = "USB2_PORT_MID(OC3)"
  48         register "usb2_ports[7]" = "USB2_PORT_MID(OC3)"
  49
  50         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
  51         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
  52         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"
  53         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"
  54
  55         register "sata_salp_support" = "1"
  56
  57         register "sata_ports_enable" = "{
  58                 [0] = 1,
  59                 [1] = 1,
  60         }"
  61
  62         register "sata_ports_dev_slp" = "{
  63                 [0] = 1,
  64                 [1] = 1,
  65         }"
  66
  67         register "serial_io_uart_mode" = "{
  68                 [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
  69                 [PchSerialIoIndexUART1] = PchSerialIoPci,
  70                 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
  71         }"
  72
  73         # Clock source 0 is shared between PCH RP 5, 6, 7, 8, 9 and CPU RP 1, 2, 3
  74         # Clock source 0 is therefore marked as FREE_RUNNING
  75         # Set PCIE_RP_CLK_SRC_UNUSED on the root ports using clock source 0 so that
  76         # we don't get a warning at boot about a missing clock definition.
  77         register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING"
  78
  79         register "pch_pcie_rp[PCH_RP(5)].flags" = "PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_LTR | PCIE_RP_AER"
  80         register "pch_pcie_rp[PCH_RP(6)].flags" = "PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_LTR | PCIE_RP_AER"
  81         register "pch_pcie_rp[PCH_RP(7)].flags" = "PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_LTR | PCIE_RP_AER"
  82         register "pch_pcie_rp[PCH_RP(8)].flags" = "PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_LTR | PCIE_RP_AER"
  83         register "pch_pcie_rp[PCH_RP(9)].flags" = "PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_LTR | PCIE_RP_AER" # UFS or general purpose RP
  84
  85         register "pch_pcie_rp[PCH_RP(5)].pcie_rp_aspm" = "ASPM_DISABLE"
  86         register "pch_pcie_rp[PCH_RP(6)].pcie_rp_aspm" = "ASPM_DISABLE"
  87         register "pch_pcie_rp[PCH_RP(7)].pcie_rp_aspm" = "ASPM_DISABLE"
  88         register "pch_pcie_rp[PCH_RP(8)].pcie_rp_aspm" = "ASPM_DISABLE"
  89         register "pch_pcie_rp[PCH_RP(9)].pcie_rp_aspm" = "ASPM_DISABLE"
  90
  91         register "pch_pcie_rp[PCH_RP(5)].PcieRpL1Substates" = "L1_SS_DISABLED"
  92         register "pch_pcie_rp[PCH_RP(6)].PcieRpL1Substates" = "L1_SS_DISABLED"
  93         register "pch_pcie_rp[PCH_RP(7)].PcieRpL1Substates" = "L1_SS_DISABLED"
  94         register "pch_pcie_rp[PCH_RP(8)].PcieRpL1Substates" = "L1_SS_DISABLED"
  95         register "pch_pcie_rp[PCH_RP(9)].PcieRpL1Substates" = "L1_SS_DISABLED"
  96
  97         # Enable PCIe-to-i225 bridge using clk 1
  98         #TODO set clk_req, once it's connected on atlas. clk_req now defaults to 0,
  99         #     because using 0xFF (unused) would trigger a bug.
 100         register "pch_pcie_rp[PCH_RP(10)]" = "{
 101                 .clk_src = 1,
 102                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN,
 103                 .pcie_rp_aspm = ASPM_AUTO,
 104         }"
 105
 106         device domain 0 on
 107                 device ref pcie5_0 on
 108                         register "cpu_pcie_rp[CPU_RP(2)].flags" = "PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED"
 109                         register "cpu_pcie_rp[CPU_RP(2)].pcie_rp_aspm" = "ASPM_AUTO"
 110                         register "cpu_pcie_rp[CPU_RP(2)].PcieRpL1Substates" = "L1_SS_DISABLED"
 111                 end
 112                 device ref igpu on end
 113                 # without DDT enabled, edk2 doesn't even finish (TODO)
 114                 device ref dtt on end
 115                 device ref pcie4_0 on
 116                         register "cpu_pcie_rp[CPU_RP(1)].flags" = "PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED"
 117                         register "cpu_pcie_rp[CPU_RP(1)].pcie_rp_aspm" = "ASPM_DISABLE"
 118                         register "cpu_pcie_rp[CPU_RP(1)].PcieRpL1Substates" = "L1_SS_DISABLED"
 119                 end
 120                 device ref pcie4_1 on
 121                         register "cpu_pcie_rp[CPU_RP(3)].flags" = "PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED"
 122                         register "cpu_pcie_rp[CPU_RP(3)].pcie_rp_aspm" = "ASPM_DISABLE"
 123                         register "cpu_pcie_rp[CPU_RP(3)].PcieRpL1Substates" = "L1_SS_DISABLED"
 124                 end
 125                 # TODO try enabling crashlog
 126                 device ref crashlog on end
 127                 device ref ish on end
 128                 device ref ufs off end
 129                 device ref tcss_xhci on end
 130                 device ref xhci on end
 131                 device ref heci1 on end
 132                 device ref sata on end
 133                 # pcie_rp[1-4] is used for USB
 134                 device ref pcie_rp5 on end
 135                 device ref pcie_rp6 on end
 136                 device ref pcie_rp7 on end
 137                 device ref pcie_rp8 on end
 138                 device ref pcie_rp9 on end
 139                 device ref pcie_rp10 on end
 140                 # pcie_rp[11-12] is used for SATA
 141                 device ref uart0 on end
 142                 device ref uart1 on end
 143                 device ref pch_espi on
 144                         chip drivers/pc80/tpm
 145                                 device pnp 0c31.0 on end
 146                         end
 147                 end
 148                 device ref p2sb on end
 149                 device ref hda on end
 150                 device ref smbus on end
 151         end
 152 end