libpayload: configs: Add new config.featuretest to broaden CI
[coreboot.git] / src / mainboard / protectli / vault_kbl / gpio.h
blob8e59db91c2eb52c552dc10054df10ab6f7c3bfc2
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #ifndef _GPIOFW6B_H
4 #define _GPIOFW6B_H
6 #include <soc/gpio.h>
8 #ifndef __ACPI__
10 /* Pad configuration in ramstage. */
11 static const struct pad_config gpio_table[] = {
12 /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
13 /* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
14 /* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
15 /* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
16 /* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
17 /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
18 /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
19 /* PIRQA_N*/ PAD_CFG_TERM_GPO(GPP_A7, 1, NONE, DEEP),
20 /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
21 /* PCH_LPC_CLK0 */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
22 /* PCH_LPC_CLK1 */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
23 /* PME# */ PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1),
24 /* ISH_GP6 */ PAD_NC(GPP_A12, NONE),
25 /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
26 /* PCH_SUSSTAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
27 /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),
28 /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE),
29 /* SD_PWR_EN */ PAD_NC(GPP_A17, NONE),
30 /* ISH_GP0 */ PAD_NC(GPP_A18, NONE),
31 /* ISH_GP1 */ PAD_NC(GPP_A19, NONE),
32 /* ISH_GP2 */ PAD_NC(GPP_A20, NONE),
33 /* ISH_GP3 */ PAD_NC(GPP_A21, NONE),
34 /* ISH_GP4 */ PAD_NC(GPP_A22, NONE),
35 /* ISH_GP5 */ PAD_NC(GPP_A23, NONE),
36 /* CORE_VID0 */ PAD_NC(GPP_B0, NONE),
37 /* CORE_VID1 */ PAD_NC(GPP_B1, NONE),
38 /* VRALERT_N */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
39 /* CPU_GP2 */ PAD_NC(GPP_B3, NONE),
40 /* CPU_GP3 */ PAD_NC(GPP_B4, NONE),
41 /* SRCCLKREQ0_N */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
42 /* SRCCLKREQ1_N*/ PAD_NC(GPP_B6, NONE),
43 /* SRCCLKREQ2_N*/ PAD_NC(GPP_B7, NONE),
44 /* SRCCLKREQ3_N*/ PAD_NC(GPP_B8, NONE),
45 /* SRCCLKREQ4_N*/ PAD_NC(GPP_B9, NONE),
46 /* SRCCLKREQ5_N*/ PAD_NC(GPP_B10, NONE),
47 /* EXT_PWR_GATE_N */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
48 /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
49 /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
50 /* SPKR */ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1),
51 /* GSPI0_CS_N */ PAD_NC(GPP_B15, NONE),
52 /* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),
53 /* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),
54 /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),
55 /* GSPI1_CS_N */ PAD_NC(GPP_B19, NONE),
56 /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE),
57 /* GSPI1_MISO */ PAD_NC(GPP_B21, NONE),
58 /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE),
59 /* SM1ALERT# */ PAD_NC(GPP_B23, NONE),
60 /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
61 /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
62 /* SMBALERT# */ PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1),
63 /* SML0_CLK */ PAD_NC(GPP_C3, NONE),
64 /* SML0DATA */ PAD_NC(GPP_C4, NONE),
65 /* SML0ALERT# */ PAD_NC(GPP_C5, NONE),
66 /* UART0_RXD */ PAD_NC(GPP_C8, NONE),
67 /* UART0_TXD */ PAD_NC(GPP_C9, NONE),
68 /* UART0_CTS_N */ PAD_NC(GPP_C10, NONE),
69 /* UART0_RTS_N */ PAD_NC(GPP_C11, NONE),
70 /* UART1_RXD */ PAD_NC(GPP_C12, NONE),
71 /* UART1_TXD */ PAD_NC(GPP_C13, NONE),
72 /* UART1_CTS_N */ PAD_NC(GPP_C14, NONE),
73 /* UART1_RTS_N */ PAD_NC(GPP_C15, NONE),
74 /* I2C0_SDA */ PAD_NC(GPP_C16, NONE),
75 /* I2C0_SCL */ PAD_NC(GPP_C17, NONE),
76 /* I2C1_SDA */ PAD_NC(GPP_C18, NONE),
77 /* I2C1_SCL */ PAD_NC(GPP_C19, NONE),
78 /* UART2_RXD */ PAD_NC(GPP_C20, NONE),
79 /* UART2_TXD */ PAD_NC(GPP_C21, NONE),
80 /* UART2_CTS_N */ PAD_NC(GPP_C22, NONE),
81 /* UART2_RTS_N */ PAD_NC(GPP_C23, NONE),
82 /* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE),
83 /* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE),
84 /* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE),
85 /* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE),
86 /* FLASHTRIG */ PAD_NC(GPP_D4, NONE),
87 /* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE),
88 /* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE),
89 /* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE),
90 /* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE),
91 /* GPP_D9 */ PAD_NC(GPP_D9, NONE),
92 /* GPP_D10 */ PAD_NC(GPP_D10, NONE),
93 /* GPP_D11 */ PAD_NC(GPP_D11, NONE),
94 /* GPP_D12 */ PAD_NC(GPP_D12, NONE),
95 /* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE),
96 /* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE),
97 /* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE),
98 /* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE),
99 /* DMIC_CLK_1 */ PAD_NC(GPP_D17, NONE),
100 /* DMIC_DATA_1 */ PAD_NC(GPP_D18, NONE),
101 /* DMIC_CLK_0 */ PAD_NC(GPP_D19, NONE),
102 /* DMIC_DATA_0 */ PAD_NC(GPP_D20, NONE),
103 /* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE),
104 /* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE),
105 /* I2S_MCLK */ PAD_NC(GPP_D23, NONE),
106 /* SATAXPCIE0 (TP8) */ PAD_NC(GPP_E0, NONE),
107 /* SATAXPCIE1 (TP9)*/ PAD_NC(GPP_E1, NONE),
108 /* SATAXPCIE2 (TP10) */ PAD_NC(GPP_E2, NONE),
109 /* CPU_GP0 */ PAD_NC(GPP_E3, NONE),
110 /* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE),
111 /* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE),
112 /* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE),
113 /* CPU_GP1 */ PAD_NC(GPP_E7, NONE),
114 /* SATA_LED */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
115 /* USB2_OC_0 */ PAD_NC(GPP_E9, NONE),
116 /* USB2_OC_1 */ PAD_NC(GPP_E10, NONE),
117 /* USB2_OC_2 */ PAD_NC(GPP_E11, NONE),
118 /* USB2_OC_3 */ PAD_NC(GPP_E12, NONE),
119 /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
120 /* DDI2_HPD */ PAD_NC(GPP_E14, NONE),
121 /* DDI3_HPD */ PAD_NC(GPP_E15, NONE),
122 /* DDI4_HPD */ PAD_NC(GPP_E16, NONE),
123 /* EDP_HPD */ PAD_NC(GPP_E17, NONE),
124 /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
125 /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
126 /* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE),
127 /* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE),
128 /* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE),
129 /* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE),
130 /* I2S2_SCLK */ PAD_NC(GPP_F0, NONE),
131 /* I2S2_SFRM */ PAD_NC(GPP_F1, NONE),
132 /* I2S2_TXD */ PAD_NC(GPP_F2, NONE),
133 /* I2S2_RXD */ PAD_NC(GPP_F3, NONE),
134 /* I2C2_SDA */ PAD_NC(GPP_F4, NONE),
135 /* I2C2_SCL */ PAD_NC(GPP_F5, NONE),
136 /* I2C3_SDA */ PAD_NC(GPP_F6, NONE),
137 /* I2C3_SCL */ PAD_NC(GPP_F7, NONE),
138 /* I2C4_SDA */ PAD_NC(GPP_F8, NONE),
139 /* I2C4_SDA */ PAD_NC(GPP_F9, NONE),
140 /* I2C5_SDA */ PAD_NC(GPP_F10, NONE),
141 /* I2C5_SCL */ PAD_NC(GPP_F11, NONE),
142 /* EMMC_CMD */ PAD_NC(GPP_F12, NONE),
143 /* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE),
144 /* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE),
145 /* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE),
146 /* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE),
147 /* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE),
148 /* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE),
149 /* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE),
150 /* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE),
151 /* EMMC_RCLK */ PAD_NC(GPP_F21, NONE),
152 /* EMMC_CLK */ PAD_NC(GPP_F22, NONE),
153 /* GPP_F23 */ PAD_NC(GPP_F23, NONE),
154 /* SD_CMD */ PAD_NC(GPP_G0, NONE),
155 /* SD_DATA0 */ PAD_NC(GPP_G1, NONE),
156 /* SD_DATA1 */ PAD_NC(GPP_G2, NONE),
157 /* SD_DATA2 */ PAD_NC(GPP_G3, NONE),
158 /* SD_DATA3 */ PAD_NC(GPP_G4, NONE),
159 /* SD_CD# */ PAD_NC(GPP_G5, NONE),
160 /* SD_CLK */ PAD_NC(GPP_G6, NONE),
161 /* SD_WP */ PAD_NC(GPP_G7, NONE),
162 /* PCH_BATLOW */ PAD_NC(GPD0, NONE),
163 /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
164 /* LAN_WAKE_N */ PAD_NC(GPD2, NONE),
165 /* PWRBTN */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
166 /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
167 /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
168 /* PM_SLP_SA# (TP7) */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
169 /* GPD7_RSVD */ PAD_CFG_TERM_GPO(GPD7, 1, NONE, DEEP),
170 /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
171 /* SLP_WLAN# (TP6) */ PAD_NC(GPD9, NONE),
172 /* SLP_S5# (TP3) */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
173 /* LANPHYC */ PAD_NC(GPD11, NONE),
176 #endif
178 #endif