src/mainboard/starlabs/starfighter/variants/rpl/devtree.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <chip.h>
   4 #include <cpu/intel/turbo.h>
   5 #include <device/device.h>
   6 #include <device/pci_def.h>
   7 #include <option.h>
   8 #include <static.h>
   9 #include <types.h>
  10 #include <variants.h>
  11
  12 void devtree_update(void)
  13 {
  14         config_t *cfg = config_of_soc();
  15
  16         struct soc_intel_common_config *common_config;
  17         common_config = chip_get_common_soc_structure();
  18
  19         struct soc_power_limits_config *soc_conf_6core =
  20                 &cfg->power_limits_config[RPL_P_282_242_142_15W_CORE];
  21
  22         struct soc_power_limits_config *soc_conf_14core =
  23                 &cfg->power_limits_config[RPL_P_682_642_482_45W_CORE];
  24
  25         struct device *tbt_pci_dev_0 = pcidev_on_root(0x07, 0);
  26         struct device *tbt_pci_dev_1 = pcidev_on_root(0x07, 0);
  27         struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2);
  28         struct device *gna_dev = pcidev_on_root(0x08, 0);
  29
  30         uint8_t performance_scale = 100;
  31
  32         /* Set PL4 to 1.0C */
  33         soc_conf_6core->tdp_pl4                         = 65;
  34         soc_conf_14core->tdp_pl4                        = 65;
  35
  36         /* Set PL1 to 50% of PL2 */
  37         soc_conf_6core->tdp_pl1_override = (soc_conf_6core->tdp_pl2_override / 2) & ~1;
  38         soc_conf_14core->tdp_pl1_override = (soc_conf_14core->tdp_pl2_override / 2) & ~1;
  39
  40         /* Scale PL1 & PL2 based on CMOS settings */
  41         switch (get_power_profile(PP_POWER_SAVER)) {
  42         case PP_POWER_SAVER:
  43                 performance_scale                       -= 50;
  44                 common_config->pch_thermal_trip         = 30;
  45                 break;
  46         case PP_BALANCED:
  47                 performance_scale                       -= 25;
  48                 common_config->pch_thermal_trip         = 25;
  49                 break;
  50         case PP_PERFORMANCE:
  51                 /* Use the Intel defaults */
  52                 common_config->pch_thermal_trip         = 20;
  53                 break;
  54         }
  55
  56         soc_conf_6core->tdp_pl1_override = (soc_conf_6core->tdp_pl1_override * performance_scale) / 100;
  57         soc_conf_6core->tdp_pl2_override = (soc_conf_6core->tdp_pl2_override * performance_scale) / 100;
  58
  59         soc_conf_14core->tdp_pl1_override = (soc_conf_14core->tdp_pl1_override * performance_scale) / 100;
  60         soc_conf_14core->tdp_pl2_override = (soc_conf_14core->tdp_pl2_override * performance_scale) / 100;
  61
  62         /* Enable/Disable Bluetooth based on CMOS settings */
  63         if (get_uint_option("wireless", 1) == 0)
  64                 cfg->usb2_ports[9].enable = 0;
  65
  66         /* Enable/Disable Webcam based on CMOS settings */
  67         if (get_uint_option("webcam", 1) == 0)
  68                 cfg->usb2_ports[CONFIG_CCD_PORT].enable = 0;
  69
  70         /* Enable/Disable Thunderbolt based on CMOS settings */
  71         if (get_uint_option("thunderbolt", 1) == 0) {
  72                 tbt_pci_dev_0->enabled = 0;
  73                 tbt_pci_dev_1->enabled = 0;
  74                 tbt_dma_dev->enabled = 0;
  75         }
  76
  77         /* Enable/Disable GNA based on CMOS settings */
  78         if (get_uint_option("gna", 0) == 0)
  79                 gna_dev->enabled = 0;
  80 }