src/mainboard/system76/cml-u/variants/galp4/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <mainboard/gpio.h>
   4 #include <soc/gpio.h>
   5
   6 static const struct pad_config gpio_table[] = {
   7         /* ------- GPIO Group GPD ------- */
   8         PAD_NC(GPD0, NONE), // PM_BATLOW#
   9         PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
  10         PAD_NC(GPD2, NONE),
  11         PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
  12         PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
  13         PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
  14         PAD_NC(GPD6, NONE),
  15         PAD_CFG_GPI(GPD7, NONE, DEEP), // 100k pull up
  16         PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
  17         PAD_NC(GPD9, NONE), // GPD9_RTD3
  18         PAD_NC(GPD10, NONE),
  19         PAD_NC(GPD11, NONE),
  20
  21         /* ------- GPIO Group A ------- */
  22         PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
  23         PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
  24         PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
  25         PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
  26         PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
  27         PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
  28         PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ with 10k pull up
  29         PAD_CFG_GPI(GPP_A7, NONE, DEEP), // TPM_PIRQ#
  30         PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# with 8.2k pull-up
  31         PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC
  32         PAD_NC(GPP_A10, NONE),
  33         PAD_NC(GPP_A11, NONE),
  34         PAD_NC(GPP_A12, NONE), // PCH_GPP_A12
  35         PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
  36         PAD_NC(GPP_A14, NONE),
  37         PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK
  38         PAD_NC(GPP_A16, NONE),
  39         PAD_CFG_GPI(GPP_A17, NONE, DEEP), // LIGHT_KB_DET#
  40         PAD_NC(GPP_A18, NONE),
  41         PAD_CFG_GPO(GPP_A19, 1, DEEP), // SATA_PWR_EN
  42         PAD_NC(GPP_A20, NONE),
  43         PAD_NC(GPP_A21, NONE),
  44         PAD_CFG_GPO(GPP_A22, 0, DEEP), // PS8338B_SW
  45         PAD_CFG_GPO(GPP_A23, 0, DEEP), // PS8338B_PCH
  46
  47         /* ------- GPIO Group B ------- */
  48         PAD_NC(GPP_B0, NONE), // CORE_VID0
  49         PAD_NC(GPP_B1, NONE), // CORE_VID1
  50         PAD_CFG_GPO(GPP_B2, 0, DEEP), // CNVI_WAKE#
  51         PAD_NC(GPP_B3, NONE),
  52         PAD_NC(GPP_B4, NONE),
  53         PAD_NC(GPP_B5, NONE),
  54         PAD_NC(GPP_B6, NONE),
  55         PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ#
  56         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // LAN_CLKREQ#
  57         PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // TBT_CLKREQ#
  58         PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // SSD_CLKREQ#
  59         PAD_NC(GPP_B11, NONE), // EXT_PWR_GATE#
  60         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# with 100k pull down
  61         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
  62         PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
  63         PAD_NC(GPP_B15, NONE),
  64         PAD_NC(GPP_B16, NONE), // PCH_GPP_B16
  65         PAD_NC(GPP_B17, NONE), // PCH_GPP_B17
  66         PAD_NC(GPP_B18, NONE), // PCH_GPP_B18 - strap for disabling no reboot mode
  67         PAD_NC(GPP_B19, NONE),
  68         PAD_NC(GPP_B20, NONE),
  69         PAD_NC(GPP_B21, NONE),
  70         PAD_NC(GPP_B22, NONE), // PCH_GPP_B22
  71         PAD_NC(GPP_B23, NONE),
  72
  73         /* ------- GPIO Group C ------- */
  74         PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR
  75         PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT_DDR
  76         PAD_NC(GPP_C2, NONE), // PCH_GPP_C2 with 4.7k pull-up
  77         PAD_NC(GPP_C3, NONE),
  78         PAD_NC(GPP_C4, NONE),
  79         PAD_NC(GPP_C5, NONE), // PCH_GPP_C5 with 4.7k pull down
  80         PAD_CFG_GPI(GPP_C6, NONE, DEEP), // LAN_WAKEUP#
  81         PAD_NC(GPP_C7, NONE),
  82         PAD_NC(GPP_C8, NONE),
  83         _PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000), // TBCIO_PLUG_EVENT
  84         PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST), // TBT_FRC_PWR
  85         PAD_NC(GPP_C11, NONE),
  86         PAD_CFG_GPO(GPP_C12, 1, PLTRST), // GPP_C12_RTD3
  87         PAD_CFG_GPO(GPP_C13, 1, PLTRST), // SSD_PWR_DN#
  88         PAD_CFG_GPO(GPP_C14, 0, PLTRST), // TBTA_HRESET
  89         PAD_CFG_GPO(GPP_C15, 1, PLTRST), // TBT_PERST_N
  90         PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // T_SDA
  91         PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // T_SCL
  92         PAD_NC(GPP_C18, NONE),
  93         PAD_NC(GPP_C19, NONE), // SWI# on galp4, NC on darp6
  94         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
  95         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
  96         PAD_NC(GPP_C22, NONE),
  97         PAD_CFG_GPI_APIC_LOW(GPP_C23, NONE, PLTRST), // NC on galp4, TP_ATTN# on darp6
  98
  99         /* ------- GPIO Group D ------- */
 100         PAD_NC(GPP_D0, NONE),
 101         PAD_NC(GPP_D1, NONE),
 102         PAD_NC(GPP_D2, NONE),
 103         PAD_NC(GPP_D3, NONE),
 104         PAD_NC(GPP_D4, NONE),
 105         PAD_NC(GPP_D5, NONE),
 106         PAD_NC(GPP_D6, NONE),
 107         PAD_NC(GPP_D7, NONE),
 108         PAD_CFG_GPO(GPP_D8, 1, DEEP), // SB_BLON
 109         _PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000), // SWI#
 110         PAD_NC(GPP_D10, NONE),
 111         _PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000), // RTD3_PCIE_WAKE#
 112         PAD_NC(GPP_D12, NONE), // PCH_GPP_D12
 113         PAD_NC(GPP_D13, NONE),
 114         PAD_NC(GPP_D14, NONE),
 115         PAD_CFG_GPO(GPP_D15, 1, DEEP), // TBT_RTD3_PWR_EN_D15 on galp4, NC on darp6
 116         PAD_CFG_GPO(GPP_D16, 1, PWROK), // RTD3_3G_PW R_EN on galp4, NC on darp6
 117         PAD_NC(GPP_D17, NONE),
 118         PAD_NC(GPP_D18, NONE),
 119         PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // GPPC_DMIC_CLK
 120         PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // GPPC_DMIC_DATA
 121         PAD_CFG_GPI(GPP_D21, NONE, DEEP), // TPM_DET#
 122         PAD_CFG_GPI(GPP_D22, NONE, DEEP), // TPM_TCM_Detect
 123         PAD_NC(GPP_D23, NONE),
 124
 125         /* ------- GPIO Group E ------- */
 126         PAD_NC(GPP_E0, NONE), // PCH_GPP_E0 with 10k pull-up
 127         PAD_NC(GPP_E1, NONE), // SATA_ODD_PRSNT#
 128         PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), // SATAGP2
 129         PAD_NC(GPP_E3, NONE),
 130         PAD_NC(GPP_E4, NONE),
 131         PAD_NC(GPP_E5, NONE),
 132         PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // DEVSLP2
 133         PAD_NC(GPP_E7, NONE),
 134         PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
 135         PAD_NC(GPP_E9, NONE), // GP_BSSB_CLK
 136         PAD_NC(GPP_E10, NONE), // GPP_E10
 137         PAD_NC(GPP_E11, NONE), // GPP_E11
 138         PAD_NC(GPP_E12, NONE), // USB_OC#78
 139         PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), // MUX_HPD
 140         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // HDMI_HPD
 141         _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), // SMI#
 142         _PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000), // SCI#
 143         PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), // EDP_HPD
 144         PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), // MDP_CTRLCLK
 145         PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), // MDP_CTRLDATA
 146         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), // HDMI_CTRLCLK
 147         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), // HDMI_CTRLDATA
 148         PAD_NC(GPP_E22, NONE),
 149         PAD_NC(GPP_E23, NONE),
 150
 151         /* ------- GPIO Group F ------- */
 152         PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
 153         PAD_NC(GPP_F1, NONE),
 154         PAD_NC(GPP_F2, NONE),
 155         PAD_NC(GPP_F3, NONE),
 156         PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_BRI_DT
 157         PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
 158         PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_RGI_DT
 159         PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
 160         PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
 161         PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
 162         PAD_NC(GPP_F10, NONE),
 163         PAD_NC(GPP_F11, NONE),
 164         PAD_NC(GPP_F12, NONE),
 165         PAD_NC(GPP_F13, NONE),
 166         PAD_NC(GPP_F14, NONE),
 167         PAD_NC(GPP_F15, NONE),
 168         PAD_NC(GPP_F16, NONE),
 169         PAD_NC(GPP_F17, NONE),
 170         PAD_NC(GPP_F18, NONE),
 171         PAD_NC(GPP_F19, NONE),
 172         PAD_NC(GPP_F20, NONE),
 173         PAD_NC(GPP_F21, NONE),
 174         PAD_NC(GPP_F22, NONE),
 175         PAD_CFG_GPI(GPP_F23, NONE, DEEP), // A4WP_PRESENT
 176
 177         /* ------- GPIO Group G ------- */
 178         PAD_CFG_GPI(GPP_G0, NONE, DEEP), // EDP_DET
 179         PAD_NC(GPP_G1, NONE),
 180         PAD_NC(GPP_G2, NONE),
 181         PAD_CFG_GPO(GPP_G3, 0, DEEP), // ASM1543_I_SEL0
 182         PAD_CFG_GPO(GPP_G4, 0, DEEP), // ASM1543_I_SEL1
 183         PAD_NC(GPP_G5, NONE), // BOARD_ID
 184         PAD_NC(GPP_G6, NONE),
 185         PAD_NC(GPP_G7, NONE), // TBT_Detect
 186
 187         /* ------- GPIO Group H ------- */
 188         PAD_NC(GPP_H0, NONE),
 189         PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), // CNVI_RST#
 190         PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), // CNVI_CLKREQ
 191         PAD_NC(GPP_H3, NONE),
 192         PAD_NC(GPP_H4, NONE),
 193         PAD_NC(GPP_H5, NONE),
 194         PAD_NC(GPP_H6, NONE),
 195         PAD_NC(GPP_H7, NONE),
 196         PAD_NC(GPP_H8, NONE),
 197         PAD_NC(GPP_H9, NONE),
 198         PAD_NC(GPP_H10, NONE),
 199         PAD_NC(GPP_H11, NONE),
 200         PAD_NC(GPP_H12, NONE),
 201         PAD_NC(GPP_H13, NONE),
 202         PAD_NC(GPP_H14, NONE), // G_INT1
 203         PAD_NC(GPP_H15, NONE),
 204         PAD_NC(GPP_H16, NONE),
 205         PAD_NC(GPP_H17, NONE),
 206         PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
 207         PAD_NC(GPP_H19, NONE),
 208         PAD_NC(GPP_H20, NONE),
 209         PAD_NC(GPP_H21, NONE), // GPPC_H21
 210         PAD_CFG_GPO(GPP_H22, 1, DEEP), // TBT_RTD3_PWR_EN_H22
 211         PAD_NC(GPP_H23, NONE), // WIGIG_PEWAKE on galp4, NC on darp6
 212 };
 213
 214 void mainboard_configure_gpios(void)
 215 {
 216         gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 217 }