src/soc/amd/mendocino/fsp_m_params.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* TODO: Check if this is still correct */
   4
   5 #include <amdblocks/apob_cache.h>
   6 #include <amdblocks/ioapic.h>
   7 #include <amdblocks/memmap.h>
   8 #include <assert.h>
   9 #include <console/console.h>
  10 #include <console/uart.h>
  11 #include <device/device.h>
  12 #include <fsp/api.h>
  13 #include <soc/platform_descriptors.h>
  14 #include <soc/pci_devs.h>
  15 #include <static.h>
  16 #include <string.h>
  17 #include <types.h>
  18 #include <vendorcode/amd/fsp/mendocino/FspUsb.h>
  19 #include "chip.h"
  20
  21 __weak void mb_pre_fspm(FSP_M_CONFIG *mcfg)
  22 {
  23 }
  24
  25 static void fill_dxio_descriptors(FSP_M_CONFIG *mcfg,
  26                         const fsp_dxio_descriptor *descs, size_t num)
  27 {
  28         size_t i;
  29
  30         ASSERT_MSG(num <= FSPM_UPD_DXIO_DESCRIPTOR_COUNT,
  31                         "Too many DXIO descriptors provided.");
  32
  33         for (i = 0; i < num; i++) {
  34                 memcpy(mcfg->dxio_descriptor[i], &descs[i], sizeof(mcfg->dxio_descriptor[0]));
  35         }
  36 }
  37
  38 static void fill_ddi_descriptors(FSP_M_CONFIG *mcfg,
  39                         const fsp_ddi_descriptor *descs, size_t num)
  40 {
  41         size_t i;
  42
  43         ASSERT_MSG(num <= FSPM_UPD_DDI_DESCRIPTOR_COUNT,
  44                         "Too many DDI descriptors provided.");
  45
  46         for (i = 0; i < num; i++) {
  47                 memcpy(&mcfg->ddi_descriptor[i], &descs[i], sizeof(mcfg->ddi_descriptor[0]));
  48         }
  49 }
  50
  51 static void fsp_fill_pcie_ddi_descriptors(FSP_M_CONFIG *mcfg)
  52 {
  53         const fsp_dxio_descriptor *fsp_dxio = NULL;
  54         const fsp_ddi_descriptor *fsp_ddi = NULL;
  55         size_t num_dxio = 0;
  56         size_t num_ddi = 0;
  57
  58         mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio,
  59                                                 &fsp_ddi, &num_ddi);
  60         fill_dxio_descriptors(mcfg, fsp_dxio, num_dxio);
  61         fill_ddi_descriptors(mcfg, fsp_ddi, num_ddi);
  62 }
  63
  64 static void fsp_assign_ioapic_upds(FSP_M_CONFIG *mcfg)
  65 {
  66         mcfg->gnb_ioapic_base = GNB_IO_APIC_ADDR;
  67         mcfg->gnb_ioapic_id = GNB_IOAPIC_ID;
  68         mcfg->fch_ioapic_id = FCH_IOAPIC_ID;
  69 }
  70
  71 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
  72 {
  73         FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
  74         const struct soc_amd_mendocino_config *config = config_of_soc();
  75
  76         mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();
  77
  78         mcfg->pci_express_base_addr = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
  79         mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
  80         mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
  81         mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
  82         mcfg->serial_port_baudrate = get_uart_baudrate();
  83         mcfg->serial_port_refclk = uart_platform_refclk();
  84
  85         /* 0 is default */
  86         mcfg->ccx_down_core_mode = config->downcore_mode;
  87         mcfg->ccx_disable_smt = config->disable_smt;
  88
  89         /* when stt_control isn't 1, FSP will ignore the other stt values */
  90         mcfg->stt_control = config->stt_control;
  91         mcfg->stt_pcb_sensor_count = config->stt_pcb_sensor_count;
  92         mcfg->stt_min_limit = config->stt_min_limit;
  93         mcfg->stt_m1 = config->stt_m1;
  94         mcfg->stt_m2 = config->stt_m2;
  95         mcfg->stt_m3 = config->stt_m3;
  96         mcfg->stt_m4 = config->stt_m4;
  97         mcfg->stt_m5 = config->stt_m5;
  98         mcfg->stt_m6 = config->stt_m6;
  99         mcfg->stt_c_apu = config->stt_c_apu;
 100         mcfg->stt_c_gpu = config->stt_c_gpu;
 101         mcfg->stt_c_hs2 = config->stt_c_hs2;
 102         mcfg->stt_alpha_apu = config->stt_alpha_apu;
 103         mcfg->stt_alpha_gpu = config->stt_alpha_gpu;
 104         mcfg->stt_alpha_hs2 = config->stt_alpha_hs2;
 105         mcfg->stt_skin_temp_apu = config->stt_skin_temp_apu;
 106         mcfg->stt_skin_temp_gpu = config->stt_skin_temp_gpu;
 107         mcfg->stt_skin_temp_hs2 = config->stt_skin_temp_hs2;
 108         mcfg->stt_error_coeff = config->stt_error_coeff;
 109         mcfg->stt_error_rate_coefficient = config->stt_error_rate_coefficient;
 110
 111         /* all following fields being 0 is a valid config */
 112         mcfg->stapm_boost = config->stapm_boost;
 113         mcfg->stapm_time_constant = config->stapm_time_constant_s;
 114         mcfg->apu_only_sppt_limit = config->apu_only_sppt_limit;
 115         mcfg->sustained_power_limit = config->sustained_power_limit_mW;
 116         mcfg->fast_ppt_limit = config->fast_ppt_limit_mW;
 117         mcfg->slow_ppt_limit = config->slow_ppt_limit_mW;
 118         mcfg->slow_ppt_time_constant = config->slow_ppt_time_constant_s;
 119         mcfg->thermctl_limit = config->thermctl_limit_degreeC;
 120
 121         /* 0 is default */
 122         mcfg->smartshift_enable = config->smartshift_enable;
 123
 124         /* 0 is default */
 125         mcfg->system_configuration = config->system_configuration;
 126
 127         /* when cppc_ctrl is 0 the other values won't be used */
 128         mcfg->cppc_ctrl = config->cppc_ctrl;
 129         mcfg->cppc_perf_limit_max_range = config->cppc_perf_limit_max_range;
 130         mcfg->cppc_perf_limit_min_range = config->cppc_perf_limit_min_range;
 131         mcfg->cppc_epp_max_range = config->cppc_epp_max_range;
 132         mcfg->cppc_epp_min_range = config->cppc_epp_min_range;
 133         mcfg->cppc_preferred_cores = config->cppc_preferred_cores;
 134
 135         /* S0i3 enable */
 136         mcfg->s0i3_enable = config->s0ix_enable;
 137         mcfg->iommu_support = is_devfn_enabled(IOMMU_DEVFN);
 138
 139         /* voltage regulator telemetry settings */
 140         mcfg->telemetry_vddcrvddfull_scale_current =
 141                 config->telemetry_vddcrvddfull_scale_current_mA;
 142         mcfg->telemetry_vddcrvddoffset =
 143                 config->telemetry_vddcrvddoffset;
 144         mcfg->telemetry_vddcrsocfull_scale_current =
 145                 config->telemetry_vddcrsocfull_scale_current_mA;
 146         mcfg->telemetry_vddcrsocOffset =
 147                 config->telemetry_vddcrsocoffset;
 148
 149         /* PCIe power vs. speed */
 150         mcfg->pspp_policy = config->pspp_policy;
 151
 152         mcfg->enable_nb_azalia = is_dev_enabled(DEV_PTR(gfx_hda));
 153         mcfg->hda_enable = is_dev_enabled(DEV_PTR(hda));
 154
 155         if (config->usb_phy_custom) {
 156                 /* devicetree config is const, use local copy */
 157                 static struct usb_phy_config lcl_usb_phy;
 158                 lcl_usb_phy = config->usb_phy;
 159                 lcl_usb_phy.Version_Major = FSP_USB_STRUCT_MAJOR_VERSION;
 160                 lcl_usb_phy.Version_Minor = FSP_USB_STRUCT_MINOR_VERSION;
 161                 lcl_usb_phy.TableLength = sizeof(struct usb_phy_config);
 162                 if ((uintptr_t)&lcl_usb_phy <= UINT32_MAX) {
 163                         mcfg->usb_phy_ptr = (uint32_t)(uintptr_t)&lcl_usb_phy;
 164                 } else {
 165                         printk(BIOS_ERR, "USB PHY config struct above 4GB; can't pass USB PHY "
 166                                          "configuration to 32 bit FSP.\n");
 167                         mcfg->usb_phy_ptr = 0;
 168                 }
 169         } else {
 170                 mcfg->usb_phy_ptr = 0;
 171         }
 172
 173         mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable;
 174         mcfg->edp_panel_t8_ms = config->edp_panel_t8_ms;
 175         mcfg->edp_panel_t9_ms = config->edp_panel_t9_ms;
 176
 177         fsp_fill_pcie_ddi_descriptors(mcfg);
 178         fsp_assign_ioapic_upds(mcfg);
 179         mb_pre_fspm(mcfg);
 180
 181         mcfg->fch_usb_3_port_force_gen1 = config->usb3_port_force_gen1.usb3_port_force_gen1_en;
 182 }