src/soc/intel/alderlake/pmc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file is created based on Intel Alder Lake Processor PCH Datasheet
   5  * Document number: 621483
   6  * Chapter number: 4
   7  */
   8
   9 #include <acpi/acpigen.h>
  10 #include <console/console.h>
  11 #include <device/mmio.h>
  12 #include <device/device.h>
  13 #include <drivers/intel/pmc_mux/chip.h>
  14 #include <intelblocks/acpi.h>
  15 #include <intelblocks/pmc.h>
  16 #include <intelblocks/pmc_ipc.h>
  17 #include <intelblocks/pmclib.h>
  18 #include <intelblocks/rtc.h>
  19 #include <soc/cpu.h>
  20 #include <soc/pci_devs.h>
  21 #include <soc/pm.h>
  22 #include <soc/soc_chip.h>
  23 #include <static.h>
  24 #include <stdint.h>
  25 #include <bootstate.h>
  26
  27 #define PMC_HID         "INTC1026"
  28
  29 static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
  30 {
  31         uint32_t reg;
  32         uint8_t *pmcbase = pmc_mmio_regs();
  33
  34         printk(BIOS_DEBUG, "%sabling Deep S%c\n",
  35                 enable ? "En" : "Dis", sx + '0');
  36         reg = read32(pmcbase + offset);
  37         if (enable)
  38                 reg |= mask;
  39         else
  40                 reg &= ~mask;
  41         write32(pmcbase + offset, reg);
  42 }
  43
  44 static void config_deep_s5(int on_ac, int on_dc)
  45 {
  46         /* Treat S4 the same as S5. */
  47         config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac);
  48         config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc);
  49         config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac);
  50         config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc);
  51 }
  52
  53 static void config_deep_s3(int on_ac, int on_dc)
  54 {
  55         config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac);
  56         config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc);
  57 }
  58
  59 static void config_deep_sx(uint32_t deepsx_config)
  60 {
  61         uint32_t reg;
  62         uint8_t *pmcbase = pmc_mmio_regs();
  63
  64         reg = read32(pmcbase + DSX_CFG);
  65         reg &= ~DSX_CFG_MASK;
  66         reg |= deepsx_config;
  67         write32(pmcbase + DSX_CFG, reg);
  68 }
  69
  70 static void soc_pmc_enable(struct device *dev)
  71 {
  72         const config_t *config = config_of_soc();
  73
  74         rtc_init();
  75
  76         pmc_set_power_failure_state(true);
  77         pmc_gpe_init();
  78
  79         config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
  80         config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
  81         config_deep_sx(config->deep_sx_config);
  82 }
  83
  84 static void soc_pmc_read_resources(struct device *dev)
  85 {
  86         struct resource *res;
  87
  88         /* Add the fixed MMIO resource */
  89         mmio_range(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
  90
  91         /* Add the fixed I/O resource */
  92         res = new_resource(dev, 1);
  93         res->base = (resource_t)ACPI_BASE_ADDRESS;
  94         res->size = (resource_t)ACPI_BASE_SIZE;
  95         res->limit = res->base + res->size - 1;
  96         res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  97 }
  98
  99 static void soc_pmc_fill_ssdt(const struct device *dev)
 100 {
 101         const char *scope = acpi_device_scope(dev);
 102         const char *name = acpi_device_name(dev);
 103         if (!scope || !name)
 104                 return;
 105
 106         acpigen_write_scope(scope);
 107         acpigen_write_device(name);
 108
 109         acpigen_write_name_string("_HID", PMC_HID);
 110         acpigen_write_name_string("_DDN", "Intel(R) Alder Lake IPC Controller");
 111         acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
 112
 113         /*
 114          * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF).
 115          * The PMC gets 0xFE000000 - 0xFE00FFFF.
 116          */
 117         acpigen_write_name("_CRS");
 118         acpigen_write_resourcetemplate_header();
 119         acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
 120         acpigen_write_resourcetemplate_footer();
 121
 122         /* Define IPC Write Method */
 123         if (CONFIG(PMC_IPC_ACPI_INTERFACE))
 124                 pmc_ipc_acpi_fill_ssdt();
 125
 126         acpigen_pop_len(); /* PMC Device */
 127         acpigen_pop_len(); /* Scope */
 128
 129         if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)) {
 130                 const struct soc_pmc_lpm adl_pmc_lpm = {
 131                         .num_substates = 8,
 132                         .num_req_regs = 6,
 133                         .lpm_ipc_offset = 0x1000,
 134                         .req_reg_stride = 0x30,
 135                         .lpm_enable_mask = get_supported_lpm_mask(),
 136                 };
 137
 138                 generate_acpi_power_engine_with_lpm(&adl_pmc_lpm);
 139         }
 140
 141         printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name,
 142                dev_path(dev));
 143 }
 144
 145 static void soc_pmc_init(struct device *dev)
 146 {
 147         /*
 148          * pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order
 149          * to ensure the ordering does not break the assumptions that other
 150          * drivers make about ACPI mode (e.g. Chrome EC). Since it disables
 151          * ACPI mode, other drivers may take different actions based on this
 152          * (e.g. Chrome EC will flush any pending hostevent bits). Because
 153          * TGL has its PMC device available for device_operations, it can be
 154          * done from the "ops->init" callback.
 155          */
 156         pmc_set_acpi_mode();
 157
 158         /*
 159          * Disable ACPI PM timer based on Kconfig
 160          *
 161          * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
 162          * Disabling ACPI PM timer also switches off TCO
 163          */
 164         if (!CONFIG(USE_PM_ACPI_TIMER))
 165                 setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
 166 }
 167
 168 static void pm1_enable_pwrbtn_smi(void *unused)
 169 {
 170         /* Enable power button SMI after BS_DEV_INIT_CHIPS (FSP-S) is done. */
 171         pmc_update_pm1_enable(PWRBTN_EN);
 172 }
 173
 174 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
 175
 176 /*
 177  * `pmc_final` function is native implementation of equivalent events performed by
 178  * each FSP NotifyPhase() API invocations.
 179  *
 180  *
 181  * Clear PMCON status bits (Global Reset/Power Failure/Host Reset Status bits)
 182  *
 183  * Perform the PMCON status bit clear operation from `.final`
 184  * to cover any such chances where later boot stage requested a global
 185  * reset and PMCON status bit remains set.
 186  */
 187 static void pmc_final(struct device *dev)
 188 {
 189         pmc_clear_pmcon_sts();
 190 }
 191
 192 struct device_operations pmc_ops = {
 193         .read_resources   = soc_pmc_read_resources,
 194         .set_resources    = noop_set_resources,
 195         .init             = soc_pmc_init,
 196         .enable           = soc_pmc_enable,
 197 #if CONFIG(HAVE_ACPI_TABLES)
 198         .acpi_fill_ssdt   = soc_pmc_fill_ssdt,
 199 #endif
 200         .scan_bus         = scan_static_bus,
 201         .final            = pmc_final,
 202 };