src/soc/intel/baytrail/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* The devicetree parser expects chip.h to reside directly in the path
   4  * specified by the devicetree. */
   5
   6 #ifndef _BAYTRAIL_CHIP_H_
   7 #define _BAYTRAIL_CHIP_H_
   8
   9 #include <drivers/intel/gma/i915.h>
  10 #include <stdint.h>
  11
  12 struct soc_intel_baytrail_config {
  13         uint8_t enable_xdp_tap;
  14         uint8_t sata_port_map;
  15         uint8_t sata_ahci;
  16         uint8_t ide_legacy_combined;
  17         uint8_t clkreq_enable;
  18
  19         /* VR low power settings -- enable PS2 mode for gfx and core */
  20         int vnn_ps2_enable;
  21         int vcc_ps2_enable;
  22
  23         /* Disable SLP_X stretching after SUS power well loss. */
  24         int disable_slp_x_stretch_sus_fail;
  25
  26         /* USB Port Disable mask */
  27         uint16_t usb2_port_disable_mask;
  28         uint16_t usb3_port_disable_mask;
  29
  30         /* USB routing */
  31         int usb_route_to_xhci;
  32
  33         /* USB PHY settings specific to the board */
  34         uint32_t usb2_per_port_lane0;
  35         uint32_t usb2_per_port_rcomp_hs_pullup0;
  36         uint32_t usb2_per_port_lane1;
  37         uint32_t usb2_per_port_rcomp_hs_pullup1;
  38         uint32_t usb2_per_port_lane2;
  39         uint32_t usb2_per_port_rcomp_hs_pullup2;
  40         uint32_t usb2_per_port_lane3;
  41         uint32_t usb2_per_port_rcomp_hs_pullup3;
  42         uint32_t usb2_comp_bg;
  43
  44         /* LPE Audio Clock configuration. */
  45         int lpe_codec_clk_freq; /* 19 or 25 are valid. */
  46         int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */
  47
  48         /* Native SD Card controller - override controller capabilities. */
  49         uint32_t sdcard_cap_low;
  50         uint32_t sdcard_cap_high;
  51
  52         /* Enable devices in ACPI mode */
  53         int lpss_acpi_mode;
  54         int scc_acpi_mode;
  55         int lpe_acpi_mode;
  56
  57         /* Allow PCIe devices to wake system from suspend. */
  58         int pcie_wake_enable;
  59
  60         uint8_t gpu_pipea_port_select;  /* Port select: 1=DP_B 2=DP_C */
  61         uint16_t gpu_pipea_power_on_delay;
  62         uint16_t gpu_pipea_light_on_delay;
  63         uint16_t gpu_pipea_power_off_delay;
  64         uint16_t gpu_pipea_light_off_delay;
  65         uint16_t gpu_pipea_power_cycle_delay;
  66         int gpu_pipea_pwm_freq_hz;
  67
  68         uint8_t gpu_pipeb_port_select;  /* Port select: 1=DP_B 2=DP_C */
  69         uint16_t gpu_pipeb_power_on_delay;
  70         uint16_t gpu_pipeb_light_on_delay;
  71         uint16_t gpu_pipeb_power_off_delay;
  72         uint16_t gpu_pipeb_light_off_delay;
  73         uint16_t gpu_pipeb_power_cycle_delay;
  74         int gpu_pipeb_pwm_freq_hz;
  75         int disable_ddr_2x_refresh_rate;
  76
  77         struct i915_gpu_controller_info gfx;
  78 };
  79
  80 #endif /* _BAYTRAIL_CHIP_H_ */