src/soc/intel/baytrail/northcluster.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <acpi/acpigen.h>
   5 #include <device/device.h>
   6 #include <device/pci.h>
   7 #include <device/pci_ids.h>
   8 #include <stdint.h>
   9 #include <soc/iomap.h>
  10 #include <soc/iosf.h>
  11 #include <soc/pci_devs.h>
  12 #include <soc/ramstage.h>
  13
  14 /*
  15  * Host Memory Map:
  16  *
  17  * +--------------------------+ BMBOUND_HI
  18  * |     Usable DRAM          |
  19  * +--------------------------+ 4GiB
  20  * |     PCI Address Space    |
  21  * +--------------------------+ BMBOUND
  22  * |     TPM                  |
  23  * +--------------------------+ IMR2
  24  * |     TXE                  |
  25  * +--------------------------+ IMR1
  26  * |     iGD                  |
  27  * +--------------------------+
  28  * |     GTT                  |
  29  * +--------------------------+ SMMRRH, IRM0
  30  * |     TSEG                 |
  31  * +--------------------------+ SMMRRL
  32  * |     Usable DRAM          |
  33  * +--------------------------+ 0
  34  *
  35  * Note that there are really only a few regions that need to enumerated w.r.t.
  36  * coreboot's resource model:
  37  *
  38  * +--------------------------+ BMBOUND_HI
  39  * |     Cacheable/Usable     |
  40  * +--------------------------+ 4GiB
  41  *
  42  * +--------------------------+ BMBOUND
  43  * |    Uncacheable/Reserved  |
  44  * +--------------------------+ SMMRRH
  45  * |    Cacheable/Reserved    |
  46  * +--------------------------+ SMMRRL
  47  * |     Cacheable/Usable     |
  48  * +--------------------------+ 0
  49  */
  50
  51 uint32_t nc_read_top_of_low_memory(void)
  52 {
  53         static uint32_t tolm;
  54
  55         if (tolm)
  56                 return tolm;
  57
  58         tolm = iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1);
  59
  60         return tolm;
  61 }
  62
  63 static void nc_read_resources(struct device *dev)
  64 {
  65         uint64_t mmconf;
  66         uint64_t bmbound;
  67         uint64_t bmbound_hi;
  68         uint64_t smmrrh;
  69         uint64_t smmrrl;
  70         int index = 0;
  71
  72         /* Read standard PCI resources. */
  73         pci_dev_read_resources(dev);
  74
  75         /* PCIe memory-mapped config space access - 256 MiB. */
  76         mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1);
  77         mmio_range(dev, BUNIT_MMCONF_REG, mmconf, CONFIG_ECAM_MMCONF_BUS_NUMBER * MiB);
  78
  79         /* 0 -> 0xa0000 */
  80         ram_from_to(dev, index++, 0, 0xa0000);
  81
  82         /* The SMMRR registers are 1MiB granularity with smmrrh being
  83          * inclusive of the SMM region. */
  84         smmrrl = (iosf_bunit_read(BUNIT_SMRRL) & 0xffff) * MiB;
  85         smmrrh = ((iosf_bunit_read(BUNIT_SMRRH) & 0xffff) + 1) * MiB;
  86
  87         /* 0xc0000 -> smrrl - cacheable and usable */
  88         ram_from_to(dev, index++, 0xc0000, smmrrl);
  89
  90         if (smmrrh > smmrrl)
  91                 reserved_ram_from_to(dev, index++, smmrrl, smmrrh);
  92
  93         /* All address space between bmbound and smmrrh is unusable. */
  94         bmbound = nc_read_top_of_low_memory();
  95         mmio_from_to(dev, index++, smmrrh, bmbound);
  96
  97         /*
  98          * The BMBOUND_HI register matches register bits of 31:24 with address
  99          * bits of 35:28. Therefore, shift register to align properly.
 100          */
 101         bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1);
 102         bmbound_hi <<= 4;
 103         upper_ram_end(dev, index++, bmbound_hi);
 104
 105         /*
 106          * Reserve everything between A segment and 1MB:
 107          *
 108          * 0xa0000 - 0xbffff: legacy VGA
 109          * 0xc0000 - 0xfffff: RAM
 110          */
 111         mmio_from_to(dev, index++, 0xa0000, 0xc0000);
 112         reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB);
 113 }
 114
 115 static void nc_generate_ssdt(const struct device *dev)
 116 {
 117         generate_cpu_entries(dev);
 118
 119         acpigen_write_scope("\\");
 120         acpigen_write_name_dword("TOLM", nc_read_top_of_low_memory());
 121         acpigen_pop_len();
 122 }
 123
 124 static struct device_operations nc_ops = {
 125         .read_resources   = nc_read_resources,
 126         .acpi_fill_ssdt   = nc_generate_ssdt,
 127         .ops_pci          = &soc_pci_ops,
 128 };
 129
 130 static const struct pci_driver nc_driver __pci_driver = {
 131         .ops    = &nc_ops,
 132         .vendor = PCI_VID_INTEL,
 133         .device = SOC_DEVID,
 134 };