1 /* SPDX-License-Identifier: GPL-2.0-only */
4 #include <acpi/acpi_gnvs.h>
5 #include <acpi/acpigen.h>
6 #include <arch/ioapic.h>
7 #include <arch/smp/mpspec.h>
8 #include <cpu/intel/haswell/haswell.h>
9 #include <device/pci_ops.h>
10 #include <console/console.h>
11 #include <device/device.h>
13 #include <cpu/intel/turbo.h>
15 #include <soc/device_nvs.h>
16 #include <soc/iomap.h>
18 #include <soc/pci_devs.h>
20 #include <soc/systemagent.h>
21 #include <soc/intel/broadwell/chip.h>
23 static unsigned long acpi_fill_dmar(unsigned long current
)
25 struct device
*const igfx_dev
= pcidev_path_on_root(SA_DEVFN_IGD
);
26 const u32 gfxvtbar
= mchbar_read32(GFXVTBAR
) & ~0xfff;
27 const u32 vtvc0bar
= mchbar_read32(VTVC0BAR
) & ~0xfff;
28 const bool gfxvten
= mchbar_read32(GFXVTBAR
) & 0x1;
29 const bool vtvc0en
= mchbar_read32(VTVC0BAR
) & 0x1;
31 /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
33 igfx_dev
&& igfx_dev
->enabled
&&
34 gfxvtbar
&& gfxvten
&&
35 !mchbar_read32(GFXVTBAR
+ 4);
37 /* First, add DRHD entries */
39 const unsigned long tmp
= current
;
41 current
+= acpi_create_dmar_drhd_4k(current
, 0, 0, gfxvtbar
);
42 current
+= acpi_create_dmar_ds_pci(current
, 0, 2, 0);
44 acpi_dmar_drhd_fixup(tmp
, current
);
47 /* VTVC0BAR has to be set, enabled, and in 32-bit space */
48 if (vtvc0bar
&& vtvc0en
&& !mchbar_read32(VTVC0BAR
+ 4)) {
49 const unsigned long tmp
= current
;
50 current
+= acpi_create_dmar_drhd_4k(current
,
51 DRHD_INCLUDE_PCI_ALL
, 0, vtvc0bar
);
52 current
+= acpi_create_dmar_ds_ioapic_from_hw(current
,
53 IO_APIC_ADDR
, PCH_IOAPIC_PCI_BUS
, PCH_IOAPIC_PCI_SLOT
, 0);
55 for (i
= 0; i
< 8; ++i
)
56 current
+= acpi_create_dmar_ds_msi_hpet(current
,
58 PCH_HPET_PCI_SLOT
, i
);
59 acpi_dmar_drhd_fixup(tmp
, current
);
62 /* Then, add RMRR entries after all DRHD entries */
64 const unsigned long tmp
= current
;
66 const struct device
*sa_dev
= pcidev_on_root(0, 0);
68 /* Bit 0 is lock bit, not part of address */
69 const u32 tolud
= pci_read_config32(sa_dev
, TOLUD
) & ~1;
70 const u32 bgsm
= pci_read_config32(sa_dev
, BGSM
) & ~1;
72 current
+= acpi_create_dmar_rmrr(current
, 0, bgsm
, tolud
- 1);
73 current
+= acpi_create_dmar_ds_pci(current
, 0, 2, 0);
74 acpi_dmar_rmrr_fixup(tmp
, current
);
80 unsigned long northbridge_write_acpi_tables(const struct device
*const dev
,
81 unsigned long current
,
82 struct acpi_rsdp
*const rsdp
)
84 /* Create DMAR table only if we have VT-d capability. */
85 const u32 capid0_a
= pci_read_config32(dev
, CAPID0_A
);
86 if (capid0_a
& VTD_DISABLE
)
89 acpi_dmar_t
*const dmar
= (acpi_dmar_t
*)current
;
90 printk(BIOS_DEBUG
, "ACPI: * DMAR\n");
91 acpi_create_dmar(dmar
, DMAR_INTR_REMAP
, acpi_fill_dmar
);
92 current
+= dmar
->header
.length
;
93 current
= acpi_align_current(current
);
94 acpi_add_table(rsdp
, dmar
);
99 size_t size_of_dnvs(void)
101 return sizeof(struct device_nvs
);