src/soc/intel/broadwell/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <device/pci_ops.h>
   5 #include <device/pci_def.h>
   6 #include <soc/iomap.h>
   7 #include <soc/pci_devs.h>
   8 #include <soc/romstage.h>
   9 #include <soc/systemagent.h>
  10
  11 static void broadwell_setup_bars(void)
  12 {
  13         /* Set up all hardcoded northbridge BARs */
  14         pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
  15         pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
  16         pci_write_config32(HOST_BRIDGE, EPBAR,  CONFIG_FIXED_EPBAR_MMIO_BASE  | 1);
  17
  18         mchbar_write32(EDRAMBAR, EDRAM_BASE_ADDRESS | 1);
  19         mchbar_write32(GDXCBAR, GDXC_BASE_ADDRESS | 1);
  20
  21         /* Set C0000-FFFFF to access RAM on both reads and writes */
  22         pci_write_config8(HOST_BRIDGE, PAM0, 0x30);
  23         pci_write_config8(HOST_BRIDGE, PAM1, 0x33);
  24         pci_write_config8(HOST_BRIDGE, PAM2, 0x33);
  25         pci_write_config8(HOST_BRIDGE, PAM3, 0x33);
  26         pci_write_config8(HOST_BRIDGE, PAM4, 0x33);
  27         pci_write_config8(HOST_BRIDGE, PAM5, 0x33);
  28         pci_write_config8(HOST_BRIDGE, PAM6, 0x33);
  29 }
  30
  31 void systemagent_early_init(void)
  32 {
  33         const bool vtd_capable =
  34                 !(pci_read_config32(HOST_BRIDGE, CAPID0_A) & VTD_DISABLE);
  35
  36         broadwell_setup_bars();
  37
  38         /* Device enable: IGD and Mini-HD */
  39         pci_write_config32(HOST_BRIDGE, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
  40
  41         if (vtd_capable) {
  42                 /* setup BARs: zeroize top 32 bits; set enable bit */
  43                 mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
  44                 mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
  45                 mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
  46                 mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
  47
  48                 /* set PRSCAPDIS, lock GFXVTBAR policy cfg registers */
  49                 u32 reg32;
  50                 reg32 = read32p(GFXVT_BASE_ADDRESS + ARCHDIS);
  51                 write32p(GFXVT_BASE_ADDRESS + ARCHDIS,
  52                                 reg32 | DMAR_LCKDN | PRSCAPDIS);
  53                 /* lock VTVC0BAR policy cfg registers */
  54                 reg32 = read32p(VTVC0_BASE_ADDRESS + ARCHDIS);
  55                 write32p(VTVC0_BASE_ADDRESS + ARCHDIS,
  56                                 reg32 | DMAR_LCKDN);
  57         }
  58 }