src/soc/intel/broadwell/pch/early_pch.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <device/pci_def.h>
   5 #include <device/pci_ops.h>
   6 #include <device/smbus_host.h>
   7 #include <soc/iomap.h>
   8 #include <soc/lpc.h>
   9 #include <soc/pch.h>
  10 #include <soc/pci_devs.h>
  11 #include <soc/pm.h>
  12 #include <soc/rcba.h>
  13 #include <soc/romstage.h>
  14 #include <soc/intel/broadwell/pch/chip.h>
  15
  16 static void pch_route_interrupts(void)
  17 {
  18         /*
  19          *             GFX    INTA -> PIRQA (MSI)
  20          * D28IP_P1IP  PCIE   INTA -> PIRQA
  21          * D29IP_E1P   EHCI   INTA -> PIRQD
  22          * D20IP_XHCI  XHCI   INTA -> PIRQC (MSI)
  23          * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
  24          * D31IP_SMIP  SMBUS  INTB -> PIRQG
  25          * D31IP_TTIP  THRT   INTC -> PIRQA
  26          * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
  27          */
  28
  29         /* Device interrupt pin register (board specific) */
  30         RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
  31                         (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
  32         RCBA32(D29IP) = (INTA << D29IP_E1P);
  33         RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
  34                         (INTB << D28IP_P4IP);
  35         RCBA32(D27IP) = (INTA << D27IP_ZIP);
  36         RCBA32(D26IP) = (INTA << D26IP_E2P);
  37         RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
  38         RCBA32(D20IP) = (INTA << D20IP_XHCI);
  39
  40         /* Device interrupt route registers */
  41         RCBA32(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA);  /* LPC */
  42         RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD);  /* EHCI */
  43         RCBA32(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);  /* PCIE */
  44         RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG);  /* HDA */
  45         RCBA32(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH);  /* SDIO */
  46         RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA);  /* ME */
  47         RCBA32(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF);  /* SIO */
  48         RCBA32(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC);  /* XHCI */
  49 }
  50
  51 static void pch_enable_lpc(void)
  52 {
  53         /* Lookup device tree in romstage */
  54         const struct device *const dev = pcidev_on_root(0x1f, 0);
  55
  56         if (!dev || !dev->chip_info)
  57                 return;
  58
  59         const struct soc_intel_broadwell_pch_config *config = dev->chip_info;
  60
  61         pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec);
  62         pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec);
  63         pci_write_config32(PCH_DEV_LPC, LPC_GEN3_DEC, config->gen3_dec);
  64         pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec);
  65 }
  66
  67 void pch_early_init(void)
  68 {
  69         pch_route_interrupts();
  70
  71         pch_enable_lpc();
  72
  73         enable_smbus();
  74
  75         /* 8.14 Additional PCI Express Programming Steps, step #1 */
  76         pci_and_config32(_PCH_DEV(PCIE, 0), 0xf4, ~0x60);
  77         pci_or_config32(_PCH_DEV(PCIE, 0), 0xf4, 0x80);
  78         pci_or_config32(_PCH_DEV(PCIE, 0), 0xe2, 0x30);
  79 }