src/soc/intel/broadwell/pch/finalize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/pci_ops.h>
   4 #include <spi-generic.h>
   5 #include <soc/pci_devs.h>
   6 #include <soc/lpc.h>
   7 #include <soc/pch.h>
   8 #include <soc/rcba.h>
   9 #include <soc/spi.h>
  10 #include <southbridge/intel/common/spi.h>
  11
  12 void broadwell_pch_finalize(void)
  13 {
  14         spi_finalize_ops();
  15
  16         /* Lock SPIBAR */
  17         if (!CONFIG(EM100PRO_SPI_CONSOLE))
  18                 RCBA32_OR(SPIBAR_OFFSET + SPIBAR_HSFS, SPIBAR_HSFS_FLOCKDN);
  19
  20         /* TC Lockdown */
  21         RCBA32_OR(0x0050, 1 << 31);
  22
  23         /* BIOS Interface Lockdown */
  24         RCBA32_OR(GCS, 1 << 0);
  25
  26         /* Function Disable SUS Well Lockdown */
  27         RCBA8(FDSW) |= 1 << 7;
  28
  29         /* Global SMI Lock */
  30         pci_or_config16(PCH_DEV_LPC, GEN_PMCON_1, SMI_LOCK);
  31
  32         /* GEN_PMCON Lock */
  33         pci_or_config8(PCH_DEV_LPC, GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
  34
  35         /* PMSYNC */
  36         RCBA32_OR(PMSYNC_CONFIG, 1 << 31);
  37
  38         /* Lock */
  39         RCBA32_OR(0x3a6c, 0x00000001);
  40
  41         /* Read+Write this R/WO register */
  42         RCBA32(LCAP) = RCBA32(LCAP);
  43 }