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libpayload: configs: Add new config.featuretest to broaden CI
[coreboot.git] / src / soc / intel / broadwell / pch / lpc.c
blob49a36b148abc6d7ee31082e7c08b1897946c9059
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <option.h>
8 #include <pc80/isa-dma.h>
9 #include <pc80/i8259.h>
10 #include <device/pci_ops.h>
11 #include <arch/ioapic.h>
12 #include <acpi/acpi.h>
13 #include <cpu/x86/smm.h>
14 #include <soc/iomap.h>
15 #include <soc/lpc.h>
16 #include <soc/pch.h>
17 #include <soc/pci_devs.h>
18 #include <soc/pm.h>
19 #include <soc/rcba.h>
20 #include <soc/intel/broadwell/pch/chip.h>
21 #include <acpi/acpigen.h>
22 #include <southbridge/intel/common/rtc.h>
23 #include <southbridge/intel/lynxpoint/iobp.h>
24 #include <southbridge/intel/lynxpoint/lp_gpio.h>
25 #include <stdbool.h>
26
27 static void pch_enable_ioapic(struct device *dev)
28 {
29 /* Assign unique bus/dev/fn for I/O APIC */
30 pci_write_config16(dev, LPC_IBDF,
31 PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
32
33 /* affirm full set of redirection table entries ("write once") */
34 /* PCH-LP has 40 redirection entries */
35 ioapic_set_max_vectors(IO_APIC_ADDR, 40);
36
37 register_new_ioapic_gsi0(IO_APIC_ADDR);
38 }
39
40 #define ACPI_SCI_IRQ 9
41
42 void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags)
43 {
44 *gsi = ACPI_SCI_IRQ;
45 *irq = ACPI_SCI_IRQ;
46 *flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
47 }
48
49 static void enable_hpet(struct device *dev)
50 {
51 size_t i;
52
53 /* Assign unique bus/dev/fn for each HPET */
54 for (i = 0; i < 8; ++i)
55 pci_write_config16(dev, LPC_HnBDF(i),
56 PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
57 }
58
59 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
60 * 0x00 - 0000 = Reserved
61 * 0x01 - 0001 = Reserved
62 * 0x02 - 0010 = Reserved
63 * 0x03 - 0011 = IRQ3
64 * 0x04 - 0100 = IRQ4
65 * 0x05 - 0101 = IRQ5
66 * 0x06 - 0110 = IRQ6
67 * 0x07 - 0111 = IRQ7
68 * 0x08 - 1000 = Reserved
69 * 0x09 - 1001 = IRQ9
70 * 0x0A - 1010 = IRQ10
71 * 0x0B - 1011 = IRQ11
72 * 0x0C - 1100 = IRQ12
73 * 0x0D - 1101 = Reserved
74 * 0x0E - 1110 = IRQ14
75 * 0x0F - 1111 = IRQ15
76 * PIRQ[n]_ROUT[7] - PIRQ Routing Control
77 * 0x80 - The PIRQ is not routed.
78 */
79
80 static void pch_pirq_init(struct device *dev)
81 {
82 struct device *irq_dev;
83
84 const uint8_t pirq = 0x80;
85
86 pci_write_config8(dev, PIRQA_ROUT, pirq);
87 pci_write_config8(dev, PIRQB_ROUT, pirq);
88 pci_write_config8(dev, PIRQC_ROUT, pirq);
89 pci_write_config8(dev, PIRQD_ROUT, pirq);
90
91 pci_write_config8(dev, PIRQE_ROUT, pirq);
92 pci_write_config8(dev, PIRQF_ROUT, pirq);
93 pci_write_config8(dev, PIRQG_ROUT, pirq);
94 pci_write_config8(dev, PIRQH_ROUT, pirq);
95
96 for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
97 u8 int_pin = 0, int_line = 0;
98
99 if (!is_enabled_pci(irq_dev))
100 continue;
101
102 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
103
104 switch (int_pin) {
105 case 1: /* INTA# */
106 case 2: /* INTB# */
107 case 3: /* INTC# */
108 case 4: /* INTD# */
109 int_line = pirq;
110 break;
111 }
112
113 if (!int_line)
114 continue;
115
116 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
117 }
118 }
119
120 static void pch_power_options(struct device *dev)
121 {
122 u16 reg16;
123 const char *state;
124
125 /* Which state do we want to goto after g3 (power restored)?
126 * 0 == S0 Full On
127 * 1 == S5 Soft Off
128 *
129 * If the option is not existent (Laptops), use Kconfig setting.
130 */
131 const unsigned int pwr_on = get_uint_option("power_on_after_fail",
132 CONFIG_MAINBOARD_POWER_FAILURE_STATE);
133
134 reg16 = pci_read_config16(dev, GEN_PMCON_3);
135 reg16 &= 0xfffe;
136 switch (pwr_on) {
137 case MAINBOARD_POWER_OFF:
138 reg16 |= 1;
139 state = "off";
140 break;
141 case MAINBOARD_POWER_ON:
142 reg16 &= ~1;
143 state = "on";
144 break;
145 case MAINBOARD_POWER_KEEP:
146 reg16 &= ~1;
147 state = "state keep";
148 break;
149 default:
150 state = "undefined";
151 }
152
153 reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
154 reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
155
156 reg16 &= ~(1 << 10);
157 reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
158
159 reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
160
161 pci_write_config16(dev, GEN_PMCON_3, reg16);
162 printk(BIOS_INFO, "Set power %s after power failure.\n", state);
163
164 if (dev->chip_info) {
165 const struct soc_intel_broadwell_pch_config *config = dev->chip_info;
166
167 /* GPE setup based on device tree configuration */
168 enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,
169 config->gpe0_en_3, config->gpe0_en_4);
170
171 /* SMI setup based on device tree configuration */
172 enable_alt_smi(config->alt_gp_smi_en);
173 }
174 }
175
176 static void pch_misc_init(struct device *dev)
177 {
178 u8 reg8;
179 u32 reg32;
180
181 /* Prepare sleep mode */
182 reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
183 reg32 &= ~SLP_TYP;
184 reg32 |= SCI_EN;
185 outl(reg32, ACPI_BASE_ADDRESS + PM1_CNT);
186
187 /* Set up NMI on errors */
188 reg8 = inb(0x61);
189 reg8 &= ~0xf0; /* Higher nibble must be 0 */
190 reg8 |= (1 << 2); /* PCI SERR# disable for now */
191 outb(reg8, 0x61);
192
193 /* Disable NMI sources */
194 reg8 = inb(0x70);
195 reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
196 outb(reg8, 0x70);
197
198 /* Indicate DRAM init done for MRC */
199 pci_or_config8(dev, GEN_PMCON_2, 1 << 7);
200
201 /* Enable BIOS updates outside of SMM */
202 pci_and_config8(dev, BIOS_CNTL, ~(1 << 5));
203
204 /* Clear status bits to prevent unexpected wake */
205 RCBA32_OR(0x3310, 0x2f);
206
207 RCBA32_AND_OR(0x3f02, ~0xf, 0);
208
209 /* Enable PCIe Releaxed Order */
210 RCBA32_OR(0x2314, (1 << 31) | (1 << 7)),
211 RCBA32_OR(0x1114, (1 << 15) | (1 << 14)),
212
213 /* Setup SERIRQ, enable continuous mode */
214 reg8 = pci_read_config8(dev, SERIRQ_CNTL);
215 reg8 |= 1 << 7;
216
217 if (CONFIG(SERIRQ_CONTINUOUS_MODE))
218 reg8 |= 1 << 6;
219
220 pci_write_config8(dev, SERIRQ_CNTL, reg8);
221 }
222
223 /* Magic register settings for power management */
224 static void pch_pm_init_magic(struct device *dev)
225 {
226 pci_write_config8(dev, 0xa9, 0x46);
227
228 RCBA32_AND_OR(0x232c, ~1, 0);
229
230 RCBA32_OR(0x1100, 0x0000c13f);
231
232 RCBA32_AND_OR(0x2320, ~0x60, 0x10);
233
234 RCBA32(0x3314) = 0x00012fff;
235
236 RCBA32_AND_OR(0x3318, ~0x000f0330, 0x0dcf0400);
237
238 RCBA32(0x3324) = 0x04000000;
239 RCBA32(0x3368) = 0x00041400;
240 RCBA32(0x3388) = 0x3f8ddbff;
241 RCBA32(0x33ac) = 0x00007001;
242 RCBA32(0x33b0) = 0x00181900;
243 RCBA32(0x33c0) = 0x00060A00;
244 RCBA32(0x33d0) = 0x06200840;
245 RCBA32(0x3a28) = 0x01010101;
246 RCBA32(0x3a2c) = 0x040c0404;
247 RCBA32(0x3a9c) = 0x9000000a;
248 RCBA32(0x2b1c) = 0x03808033;
249 RCBA32(0x2b34) = 0x80000009;
250 RCBA32(0x3348) = 0x022ddfff;
251 RCBA32(0x334c) = 0x00000001;
252 RCBA32(0x3358) = 0x0001c000;
253 RCBA32(0x3380) = 0x3f8ddbff;
254 RCBA32(0x3384) = 0x0001c7e1;
255 RCBA32(0x338c) = 0x0001c7e1;
256 RCBA32(0x3398) = 0x0001c000;
257 RCBA32(0x33a8) = 0x00181900;
258 RCBA32(0x33dc) = 0x00080000;
259 RCBA32(0x33e0) = 0x00000001;
260 RCBA32(0x3a20) = 0x0000040c;
261 RCBA32(0x3a24) = 0x01010101;
262 RCBA32(0x3a30) = 0x01010101;
263
264 pci_update_config32(dev, 0xac, ~0x00200000, 0);
265
266 RCBA32_OR(0x0410, 0x00000003);
267 RCBA32_OR(0x2618, 0x08000000);
268 RCBA32_OR(0x2300, 0x00000002);
269 RCBA32_OR(0x2600, 0x00000008);
270
271 RCBA32(0x33b4) = 0x00007001;
272 RCBA32(0x3350) = 0x022ddfff;
273 RCBA32(0x3354) = 0x00000001;
274
275 /* Power Optimizer */
276 RCBA32_OR(0x33d4, 0x08000000);
277 RCBA32_OR(0x33c8, 0x00000080);
278
279 RCBA32(0x2b10) = 0x0000883c;
280 RCBA32(0x2b14) = 0x1e0a4616;
281 RCBA32(0x2b24) = 0x40000005;
282 RCBA32(0x2b20) = 0x0005db01;
283 RCBA32(0x3a80) = 0x05145005;
284 RCBA32(0x3a84) = 0x00001005;
285
286 RCBA32_OR(0x33d4, 0x2fff2fb1);
287 RCBA32_OR(0x33c8, 0x00008000);
288 }
289
290 static void pch_enable_mphy(void)
291 {
292 u32 gpio71_native = gpio_is_native(71);
293 u32 data_and = 0xffffffff;
294 u32 data_or = (1 << 14) | (1 << 13) | (1 << 12);
295
296 if (gpio71_native) {
297 data_or |= (1 << 0);
298 if (pch_is_wpt()) {
299 data_and &= ~((1 << 7) | (1 << 6) | (1 << 3));
300 data_or |= (1 << 5) | (1 << 4);
301
302 if (pch_is_wpt_ulx()) {
303 /* Check if SATA and USB3 MPHY are enabled */
304 u32 strap19 = pch_read_soft_strap(19);
305 strap19 &= ((1 << 31) | (1 << 30));
306 strap19 >>= 30;
307 if (strap19 == 3) {
308 data_or |= (1 << 3);
309 printk(BIOS_DEBUG, "Enable ULX MPHY PG "
310 "control in single domain\n");
311 } else if (strap19 == 0) {
312 printk(BIOS_DEBUG, "Enable ULX MPHY PG "
313 "control in split domains\n");
314 } else {
315 printk(BIOS_DEBUG, "Invalid PCH Soft "
316 "Strap 19 configuration\n");
317 }
318 } else {
319 data_or |= (1 << 3);
320 }
321 }
322 }
323
324 pch_iobp_update(0xCF000000, data_and, data_or);
325 }
326
327 static void pch_init_deep_sx(struct device *dev)
328 {
329 const struct soc_intel_broadwell_pch_config *config = dev->chip_info;
330
331 if (!config)
332 return;
333
334 if (config->deep_sx_enable_ac) {
335 RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_AC);
336 RCBA32_OR(DEEP_S5_POL, DEEP_S5_EN_AC);
337 }
338
339 if (config->deep_sx_enable_dc) {
340 RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_DC);
341 RCBA32_OR(DEEP_S5_POL, DEEP_S5_EN_DC);
342 }
343
344 if (config->deep_sx_enable_ac || config->deep_sx_enable_dc)
345 RCBA32_OR(DEEP_SX_CONFIG,
346 DEEP_SX_WAKE_PIN_EN | DEEP_SX_GP27_PIN_EN);
347 }
348
349 /* Power Management init */
350 static void pch_pm_init(struct device *dev)
351 {
352 printk(BIOS_DEBUG, "PCH PM init\n");
353
354 pch_init_deep_sx(dev);
355
356 pch_enable_mphy();
357
358 pch_pm_init_magic(dev);
359
360 if (pch_is_wpt()) {
361 RCBA32_OR(0x33e0, (1 << 4) | (1 << 1));
362 RCBA32_OR(0x2b1c, (1 << 22) | (1 << 14) | (1 << 13));
363 RCBA32(0x33e4) = 0x16bf0002;
364 RCBA32_OR(0x33e4, 0x1);
365 }
366
367 pch_iobp_update(0xCA000000, ~0UL, 0x00000009);
368
369 /* Set RCBA 0x2b1c[29]=1 if DSP disabled */
370 if (RCBA32(FD) & PCH_DISABLE_ADSPD)
371 RCBA32_OR(0x2b1c, (1 << 29));
372 }
373
374 static void pch_cg_init(struct device *dev)
375 {
376 u32 reg32;
377 u16 reg16;
378 struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
379
380 /* DMI */
381 RCBA32_OR(0x2234, 0xf);
382
383 reg16 = pci_read_config16(dev, GEN_PMCON_1);
384 reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
385 if (pch_is_wpt())
386 reg16 &= ~(1 << 11);
387 else
388 reg16 |= (1 << 11);
389 reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12);
390 reg16 |= (1 << 2); // PCI CLKRUN# Enable
391 pci_write_config16(dev, GEN_PMCON_1, reg16);
392
393 /*
394 * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1
395 * RCBA + 0x2614[23:16] = 0x20
396 * RCBA + 0x2614[30:28] = 0x0
397 * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b)
398 */
399 RCBA32_AND_OR(0x2614, ~0x64ff0000, 0x0a206500);
400
401 /* Check for 0:2.0@0x08 >= 0x0b */
402 if (pch_is_wpt() || pci_read_config8(igd_dev, 0x8) >= 0x0b)
403 RCBA32_OR(0x2614, (1 << 26));
404
405 RCBA32_OR(0x900, 0x0000031f);
406
407 reg32 = RCBA32(CG);
408 if (RCBA32(0x3454) & (1 << 4))
409 reg32 &= ~(1 << 29); // LPC Dynamic
410 else
411 reg32 |= (1 << 29); // LPC Dynamic
412 reg32 |= (1 << 31); // LP LPC
413 reg32 |= (1 << 30); // LP BLA
414 if (RCBA32(0x3454) & (1 << 4))
415 reg32 &= ~(1 << 29);
416 else
417 reg32 |= (1 << 29);
418 reg32 |= (1 << 28); // GPIO Dynamic
419 reg32 |= (1 << 27); // HPET Dynamic
420 reg32 |= (1 << 26); // Generic Platform Event Clock
421 if (RCBA32(BUC) & PCH_DISABLE_GBE)
422 reg32 |= (1 << 23); // GbE Static
423 if (RCBA32(FD) & PCH_DISABLE_HD_AUDIO)
424 reg32 |= (1 << 21); // HDA Static
425 reg32 |= (1 << 22); // HDA Dynamic
426 RCBA32(CG) = reg32;
427
428 /* PCH-LP LPC */
429 if (pch_is_wpt())
430 RCBA32_AND_OR(0x3434, ~0x1f, 0x17);
431 else
432 RCBA32_OR(0x3434, 0x7);
433
434 /* SPI */
435 RCBA32_OR(0x38c0, 0x3c07);
436
437 pch_iobp_update(0xCE00C000, ~1UL, 0x00000000);
438 }
439
440 static void pch_set_acpi_mode(void)
441 {
442 if (!acpi_is_wakeup_s3()) {
443 apm_control(APM_CNT_ACPI_DISABLE);
444 }
445 }
446
447 static void lpc_init(struct device *dev)
448 {
449 /* Legacy initialization */
450 isa_dma_init();
451 sb_rtc_init();
452 pch_misc_init(dev);
453
454 /* Interrupt configuration */
455 pch_enable_ioapic(dev);
456 pch_pirq_init(dev);
457 setup_i8259();
458 i8259_configure_irq_trigger(9, 1);
459 enable_hpet(dev);
460
461 /* Initialize power management */
462 pch_power_options(dev);
463 pch_pm_init(dev);
464 pch_cg_init(dev);
465
466 pch_set_acpi_mode();
467 }
468
469 static void pch_lpc_add_mmio_resources(struct device *dev)
470 {
471 u32 reg;
472 struct resource *res;
473 const u32 default_decode_base = IO_APIC_ADDR;
474
475 /*
476 * Just report all resources from IO-APIC base to 4GiB. Don't mark
477 * them reserved as that may upset the OS if this range is marked
478 * as reserved in the e820.
479 */
480 res = new_resource(dev, OIC);
481 res->base = default_decode_base;
482 res->size = 4ull * GiB - default_decode_base;
483 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
484
485 /* RCBA */
486 if (default_decode_base > CONFIG_FIXED_RCBA_MMIO_BASE) {
487 res = new_resource(dev, RCBA);
488 res->base = CONFIG_FIXED_RCBA_MMIO_BASE;
489 res->size = CONFIG_RCBA_LENGTH;
490 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
491 IORESOURCE_FIXED | IORESOURCE_RESERVE;
492 }
493
494 /* Check LPC Memory Decode register. */
495 reg = pci_read_config32(dev, LGMR);
496 if (reg & 1) {
497 reg &= ~0xffff;
498 if (reg < default_decode_base) {
499 res = new_resource(dev, LGMR);
500 res->base = reg;
501 res->size = 16 * 1024;
502 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
503 IORESOURCE_FIXED | IORESOURCE_RESERVE;
504 }
505 }
506 }
507
508 /* Default IO range claimed by the LPC device. The upper bound is exclusive. */
509 #define LPC_DEFAULT_IO_RANGE_LOWER 0
510 #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000
511
512 static inline int pch_io_range_in_default(int base, int size)
513 {
514 /* Does it start above the range? */
515 if (base >= LPC_DEFAULT_IO_RANGE_UPPER)
516 return 0;
517
518 /* Is it entirely contained? */
519 if (base >= LPC_DEFAULT_IO_RANGE_LOWER &&
520 (base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
521 return 1;
522
523 /* This will return not in range for partial overlaps. */
524 return 0;
525 }
526
527 /*
528 * Note: this function assumes there is no overlap with the default LPC device's
529 * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
530 */
531 static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size,
532 int index)
533 {
534 struct resource *res;
535
536 if (pch_io_range_in_default(base, size))
537 return;
538
539 res = new_resource(dev, index);
540 res->base = base;
541 res->size = size;
542 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
543 }
544
545 static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value,
546 int index)
547 {
548 /*
549 * Check if the register is enabled. If so and the base exceeds the
550 * device's default claim range add the resource.
551 */
552 if (reg_value & 1) {
553 u16 base = reg_value & 0xfffc;
554 u16 size = (0x3 | ((reg_value >> 16) & 0xfc)) + 1;
555 pch_lpc_add_io_resource(dev, base, size, index);
556 }
557 }
558
559 static void pch_lpc_add_io_resources(struct device *dev)
560 {
561 struct resource *res;
562
563 /* Add the default claimed IO range for the LPC device. */
564 res = new_resource(dev, 0);
565 res->base = LPC_DEFAULT_IO_RANGE_LOWER;
566 res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER;
567 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
568
569 /* GPIOBASE */
570 pch_lpc_add_io_resource(dev, GPIO_BASE_ADDRESS,
571 GPIO_BASE_SIZE, GPIO_BASE);
572
573 /* PMBASE */
574 pch_lpc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, PMBASE);
575
576 /* LPC Generic IO Decode range. */
577 if (dev->chip_info) {
578 const struct soc_intel_broadwell_pch_config *config = dev->chip_info;
579 pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC);
580 pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC);
581 pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC);
582 pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC);
583 }
584 }
585
586 static void pch_lpc_read_resources(struct device *dev)
587 {
588 /* Get the normal PCI resources of this device. */
589 pci_dev_read_resources(dev);
590
591 /* Add non-standard MMIO resources. */
592 pch_lpc_add_mmio_resources(dev);
593
594 /* Add IO resources. */
595 pch_lpc_add_io_resources(dev);
596 }
597
598 static unsigned long broadwell_write_acpi_tables(const struct device *device,
599 unsigned long current,
600 struct acpi_rsdp *rsdp)
601 {
602 if (CONFIG(SERIALIO_UART_CONSOLE)) {
603 current = acpi_write_dbg2_pci_uart(rsdp, current,
604 (CONFIG_UART_FOR_CONSOLE == 1) ?
605 PCH_DEV_UART1 : PCH_DEV_UART0,
606 ACPI_ACCESS_SIZE_DWORD_ACCESS);
607 }
608 return acpi_write_hpet(device, current, rsdp);
609 }
610
611 static struct device_operations device_ops = {
612 .read_resources = &pch_lpc_read_resources,
613 .set_resources = &pci_dev_set_resources,
614 .enable_resources = &pci_dev_enable_resources,
615 .write_acpi_tables = broadwell_write_acpi_tables,
616 .init = &lpc_init,
617 .scan_bus = &scan_static_bus,
618 .ops_pci = &pci_dev_ops_pci,
619 };
620
621 static const unsigned short pci_device_ids[] = {
622 PCH_LPT_LP_SAMPLE,
623 PCH_LPT_LP_PREMIUM,
624 PCH_LPT_LP_MAINSTREAM,
625 PCH_LPT_LP_VALUE,
626 PCH_WPT_HSW_U_SAMPLE,
627 PCH_WPT_BDW_U_SAMPLE,
628 PCH_WPT_BDW_U_PREMIUM,
629 PCH_WPT_BDW_U_BASE,
630 PCH_WPT_BDW_Y_SAMPLE,
631 PCH_WPT_BDW_Y_PREMIUM,
632 PCH_WPT_BDW_Y_BASE,
633 PCH_WPT_BDW_H,
634 0
635 };
636
637 static const struct pci_driver pch_lpc __pci_driver = {
638 .ops = &device_ops,
639 .vendor = PCI_VID_INTEL,
640 .devices = pci_device_ids,
641 };
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