src/soc/intel/broadwell/pch/me_status.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/pci_ops.h>
   4 #include <console/console.h>
   5 #include <device/pci.h>
   6 #include <string.h>
   7 #include <soc/pci_devs.h>
   8 #include <soc/me.h>
   9 #include <delay.h>
  10
  11 #define ARRAY_TO_ELEMENT(__array__, __index__, __default__) \
  12         (((__index__) < ARRAY_SIZE((__array__))) ? \
  13                 (__array__)[(__index__)] : \
  14                 (__default__))
  15
  16 static inline void me_read_dword_ptr(void *ptr, int offset)
  17 {
  18         u32 dword = pci_read_config32(PCH_DEV_ME, offset);
  19         memcpy(ptr, &dword, sizeof(dword));
  20 }
  21
  22 /* HFS1[3:0] Current Working State Values */
  23 static const char *me_cws_values[] = {
  24         [ME_HFS_CWS_RESET]      = "Reset",
  25         [ME_HFS_CWS_INIT]       = "Initializing",
  26         [ME_HFS_CWS_REC]        = "Recovery",
  27         [3]                     = "Unknown (3)",
  28         [4]                     = "Unknown (4)",
  29         [ME_HFS_CWS_NORMAL]     = "Normal",
  30         [ME_HFS_CWS_WAIT]       = "Platform Disable Wait",
  31         [ME_HFS_CWS_TRANS]      = "OP State Transition",
  32         [ME_HFS_CWS_INVALID]    = "Invalid CPU Plugged In",
  33         [9]                     = "Unknown (9)",
  34         [10]                    = "Unknown (10)",
  35         [11]                    = "Unknown (11)",
  36         [12]                    = "Unknown (12)",
  37         [13]                    = "Unknown (13)",
  38         [14]                    = "Unknown (14)",
  39         [15]                    = "Unknown (15)",
  40 };
  41
  42 /* HFS1[8:6] Current Operation State Values */
  43 static const char *me_opstate_values[] = {
  44         [ME_HFS_STATE_PREBOOT]  = "Preboot",
  45         [ME_HFS_STATE_M0_UMA]   = "M0 with UMA",
  46         [ME_HFS_STATE_M3]       = "M3 without UMA",
  47         [ME_HFS_STATE_M0]       = "M0 without UMA",
  48         [ME_HFS_STATE_BRINGUP]  = "Bring up",
  49         [ME_HFS_STATE_ERROR]    = "M0 without UMA but with error"
  50 };
  51
  52 /* HFS[19:16] Current Operation Mode Values */
  53 static const char *me_opmode_values[] = {
  54         [ME_HFS_MODE_NORMAL]    = "Normal",
  55         [ME_HFS_MODE_DEBUG]     = "Debug",
  56         [ME_HFS_MODE_DIS]       = "Soft Temporary Disable",
  57         [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper",
  58         [ME_HFS_MODE_OVER_MEI]  = "Security Override via MEI Message"
  59 };
  60
  61 /* HFS[15:12] Error Code Values */
  62 static const char *me_error_values[] = {
  63         [ME_HFS_ERROR_NONE]     = "No Error",
  64         [ME_HFS_ERROR_UNCAT]    = "Uncategorized Failure",
  65         [ME_HFS_ERROR_IMAGE]    = "Image Failure",
  66         [ME_HFS_ERROR_DEBUG]    = "Debug Failure"
  67 };
  68
  69 /* HFS2[31:28] ME Progress Code */
  70 static const char *me_progress_values[] = {
  71         [ME_HFS2_PHASE_ROM]             = "ROM Phase",
  72         [ME_HFS2_PHASE_BUP]             = "BUP Phase",
  73         [ME_HFS2_PHASE_UKERNEL]         = "uKernel Phase",
  74         [ME_HFS2_PHASE_POLICY]          = "Policy Module",
  75         [ME_HFS2_PHASE_MODULE_LOAD]     = "Module Loading",
  76         [ME_HFS2_PHASE_UNKNOWN]         = "Unknown",
  77         [ME_HFS2_PHASE_HOST_COMM]       = "Host Communication"
  78 };
  79
  80 /* HFS2[27:24] Power Management Event */
  81 static const char *me_pmevent_values[] = {
  82         [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] =
  83         "Clean Moff->Mx wake",
  84         [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] =
  85         "Moff->Mx wake after an error",
  86         [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] =
  87         "Clean global reset",
  88         [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] =
  89         "Global reset after an error",
  90         [ME_HFS2_PMEVENT_CLEAN_ME_RESET] =
  91         "Clean Intel ME reset",
  92         [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] =
  93         "Intel ME reset due to exception",
  94         [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] =
  95         "Pseudo-global reset",
  96         [ME_HFS2_PMEVENT_S0MO_SXM3] =
  97         "S0/M0->Sx/M3",
  98         [ME_HFS2_PMEVENT_SXM3_S0M0] =
  99         "Sx/M3->S0/M0",
 100         [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] =
 101         "Non-power cycle reset",
 102         [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] =
 103         "Power cycle reset through M3",
 104         [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] =
 105         "Power cycle reset through Moff",
 106         [ME_HFS2_PMEVENT_SXMX_SXMOFF] =
 107         "Sx/Mx->Sx/Moff"
 108 };
 109
 110 /* Progress Code 0 states */
 111 static const char *me_progress_rom_values[] = {
 112         [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN",
 113         [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE"
 114 };
 115
 116 /* Progress Code 1 states */
 117 static const char *me_progress_bup_values[] = {
 118         [ME_HFS2_STATE_BUP_INIT] =
 119         "Initialization starts",
 120         [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] =
 121         "Disable the host wake event",
 122         [ME_HFS2_STATE_BUP_FLOW_DET] =
 123         "Flow determination start process",
 124         [ME_HFS2_STATE_BUP_VSCC_ERR] =
 125         "Error reading/matching the VSCC table in the descriptor",
 126         [ME_HFS2_STATE_BUP_CHECK_STRAP] =
 127         "Check to see if straps say ME DISABLED",
 128         [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] =
 129         "Timeout waiting for PWROK",
 130         [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] =
 131         "Possibly handle BUP manufacturing override strap",
 132         [ME_HFS2_STATE_BUP_M3] =
 133         "Bringup in M3",
 134         [ME_HFS2_STATE_BUP_M0] =
 135         "Bringup in M0",
 136         [ME_HFS2_STATE_BUP_FLOW_DET_ERR] =
 137         "Flow detection error",
 138         [ME_HFS2_STATE_BUP_M3_CLK_ERR] =
 139         "M3 clock switching error",
 140         [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] =
 141         "Host error - CPU reset timeout, DID timeout, memory missing",
 142         [ME_HFS2_STATE_BUP_M3_KERN_LOAD] =
 143         "M3 kernel load",
 144         [ME_HFS2_STATE_BUP_T32_MISSING] =
 145         "T34 missing - cannot program ICC",
 146         [ME_HFS2_STATE_BUP_WAIT_DID] =
 147         "Waiting for DID BIOS message",
 148         [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] =
 149         "Waiting for DID BIOS message failure",
 150         [ME_HFS2_STATE_BUP_DID_NO_FAIL] =
 151         "DID reported no error",
 152         [ME_HFS2_STATE_BUP_ENABLE_UMA] =
 153         "Enabling UMA",
 154         [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] =
 155         "Enabling UMA error",
 156         [ME_HFS2_STATE_BUP_SEND_DID_ACK] =
 157         "Sending DID Ack to BIOS",
 158         [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] =
 159         "Sending DID Ack to BIOS error",
 160         [ME_HFS2_STATE_BUP_M0_CLK] =
 161         "Switching clocks in M0",
 162         [ME_HFS2_STATE_BUP_M0_CLK_ERR] =
 163         "Switching clocks in M0 error",
 164         [ME_HFS2_STATE_BUP_TEMP_DIS] =
 165         "ME in temp disable",
 166         [ME_HFS2_STATE_BUP_M0_KERN_LOAD] =
 167         "M0 kernel load",
 168 };
 169
 170 /* Progress Code 3 states */
 171 static const char *me_progress_policy_values[] = {
 172         [ME_HFS2_STATE_POLICY_ENTRY] = "Entry into Policy Module",
 173         [ME_HFS2_STATE_POLICY_RCVD_S3] = "Received S3 entry",
 174         [ME_HFS2_STATE_POLICY_RCVD_S4] = "Received S4 entry",
 175         [ME_HFS2_STATE_POLICY_RCVD_S5] = "Received S5 entry",
 176         [ME_HFS2_STATE_POLICY_RCVD_UPD] = "Received UPD entry",
 177         [ME_HFS2_STATE_POLICY_RCVD_PCR] = "Received PCR entry",
 178         [ME_HFS2_STATE_POLICY_RCVD_NPCR] = "Received NPCR entry",
 179         [ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE] = "Received host wake",
 180         [ME_HFS2_STATE_POLICY_RCVD_AC_DC] = "Received AC<>DC switch",
 181         [ME_HFS2_STATE_POLICY_RCVD_DID] = "Received DRAM Init Done",
 182         [ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND] =
 183         "VSCC Data not found for flash device",
 184         [ME_HFS2_STATE_POLICY_VSCC_INVALID] =
 185         "VSCC Table is not valid",
 186         [ME_HFS2_STATE_POLICY_FPB_ERR] =
 187         "Flash Partition Boundary is outside address space",
 188         [ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR] =
 189         "ME cannot access the chipset descriptor region",
 190         [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] =
 191         "Required VSCC values for flash parts do not match",
 192 };
 193
 194 void intel_me_status(void)
 195 {
 196         if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG)
 197                 return;
 198
 199         struct me_hfs _hfs, *hfs = &_hfs;
 200         struct me_hfs2 _hfs2, *hfs2 = &_hfs2;
 201
 202         me_read_dword_ptr(hfs, PCI_ME_HFS);
 203         me_read_dword_ptr(hfs2, PCI_ME_HFS2);
 204
 205         /* Check Current States */
 206         printk(BIOS_DEBUG, "ME: FW Partition Table      : %s\n",
 207                hfs->fpt_bad ? "BAD" : "OK");
 208         printk(BIOS_DEBUG, "ME: Bringup Loader Failure  : %s\n",
 209                hfs->ft_bup_ld_flr ? "YES" : "NO");
 210         printk(BIOS_DEBUG, "ME: Firmware Init Complete  : %s\n",
 211                hfs->fw_init_complete ? "YES" : "NO");
 212         printk(BIOS_DEBUG, "ME: Manufacturing Mode      : %s\n",
 213                hfs->mfg_mode ? "YES" : "NO");
 214         printk(BIOS_DEBUG, "ME: Boot Options Present    : %s\n",
 215                hfs->boot_options_present ? "YES" : "NO");
 216         printk(BIOS_DEBUG, "ME: Update In Progress      : %s\n",
 217                hfs->update_in_progress ? "YES" : "NO");
 218         printk(BIOS_DEBUG, "ME: Current Working State   : %s\n",
 219                ARRAY_TO_ELEMENT(me_cws_values,
 220                                 hfs->working_state,
 221                                 "Unknown (OOB)"));
 222         printk(BIOS_DEBUG, "ME: Current Operation State : %s\n",
 223                ARRAY_TO_ELEMENT(me_opstate_values,
 224                                 hfs->operation_state,
 225                                 "Unknown (OOB)"));
 226         printk(BIOS_DEBUG, "ME: Current Operation Mode  : %s\n",
 227                ARRAY_TO_ELEMENT(me_opmode_values,
 228                                 hfs->operation_mode,
 229                                 "Unknown (OOB)"));
 230         printk(BIOS_DEBUG, "ME: Error Code              : %s\n",
 231                ARRAY_TO_ELEMENT(me_error_values,
 232                                 hfs->error_code,
 233                                 "Unknown (OOB)"));
 234         printk(BIOS_DEBUG, "ME: Progress Phase          : %s\n",
 235                ARRAY_TO_ELEMENT(me_progress_values,
 236                                 hfs2->progress_code,
 237                                 "Unknown (OOB)"));
 238         printk(BIOS_DEBUG, "ME: Power Management Event  : %s\n",
 239                ARRAY_TO_ELEMENT(me_pmevent_values,
 240                                 hfs2->current_pmevent,
 241                                 "Unknown (OOB)"));
 242
 243         printk(BIOS_DEBUG, "ME: Progress Phase State    : ");
 244         switch (hfs2->progress_code) {
 245         case ME_HFS2_PHASE_ROM:         /* ROM Phase */
 246                 printk(BIOS_DEBUG, "%s",
 247                        ARRAY_TO_ELEMENT(me_progress_rom_values,
 248                                         hfs2->current_state,
 249                                         "Unknown (OOB)"));
 250                 break;
 251
 252         case ME_HFS2_PHASE_UKERNEL:     /* uKernel Phase */
 253                 printk(BIOS_DEBUG, "0x%02x", hfs2->current_state);
 254                 break;
 255
 256         case ME_HFS2_PHASE_BUP:         /* Bringup Phase */
 257                 if (ARRAY_TO_ELEMENT(me_progress_bup_values,
 258                                         hfs2->current_state, NULL))
 259                         printk(BIOS_DEBUG, "%s",
 260                                ARRAY_TO_ELEMENT(me_progress_bup_values,
 261                                                 hfs2->current_state,
 262                                                 NULL));
 263                 else
 264                         printk(BIOS_DEBUG, "0x%02x", hfs2->current_state);
 265                 break;
 266
 267         case ME_HFS2_PHASE_POLICY:      /* Policy Module Phase */
 268                 if (ARRAY_TO_ELEMENT(me_progress_policy_values,
 269                                         hfs2->current_state, NULL))
 270                         printk(BIOS_DEBUG, "%s",
 271                                ARRAY_TO_ELEMENT(me_progress_policy_values,
 272                                                 hfs2->current_state,
 273                                                 NULL));
 274                 else
 275                         printk(BIOS_DEBUG, "0x%02x", hfs2->current_state);
 276                 break;
 277
 278         case ME_HFS2_PHASE_HOST_COMM:   /* Host Communication Phase */
 279                 if (!hfs2->current_state)
 280                         printk(BIOS_DEBUG, "Host communication established");
 281                 else
 282                         printk(BIOS_DEBUG, "0x%02x", hfs2->current_state);
 283                 break;
 284
 285         default:
 286                 printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x",
 287                        hfs2->progress_code, hfs2->current_state);
 288         }
 289         printk(BIOS_DEBUG, "\n");
 290 }
 291
 292 void intel_me_hsio_version(uint16_t *version, uint16_t *checksum)
 293 {
 294         int count;
 295         u32 hsiover;
 296         struct me_hfs hfs;
 297
 298         /* Query for HSIO version, overloads H_GS and HFS */
 299         pci_write_config32(PCH_DEV_ME, PCI_ME_H_GS,
 300                            ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
 301
 302         /* Must wait for ME acknowledgement */
 303         for (count = ME_RETRY; count > 0; --count) {
 304                 me_read_dword_ptr(&hfs, PCI_ME_HFS);
 305                 if (hfs.bios_msg_ack)
 306                         break;
 307                 udelay(ME_DELAY);
 308         }
 309         if (!count) {
 310                 printk(BIOS_ERR, "ME failed to respond\n");
 311                 return;
 312         }
 313
 314         /* HSIO version should be in HFS_5 */
 315         hsiover = pci_read_config32(PCH_DEV_ME, PCI_ME_HFS5);
 316         *version = hsiover >> 16;
 317         *checksum = hsiover & 0xffff;
 318
 319         printk(BIOS_DEBUG, "ME: HSIO Version            : %d (CRC 0x%04x)\n",
 320                *version, *checksum);
 321
 322         /* Reset registers to normal behavior */
 323         pci_write_config32(PCH_DEV_ME, PCI_ME_H_GS,
 324                            ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
 325 }