src/soc/intel/broadwell/pch/serialio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <device/pci_ops.h>
   5 #include <acpi/acpi_gnvs.h>
   6 #include <console/console.h>
   7 #include <device/device.h>
   8 #include <device/pci.h>
   9 #include <device/pci_ids.h>
  10 #include <soc/device_nvs.h>
  11 #include <soc/pci_devs.h>
  12 #include <soc/pch.h>
  13 #include <soc/rcba.h>
  14 #include <soc/serialio.h>
  15 #include <soc/intel/broadwell/pch/chip.h>
  16 #include <southbridge/intel/lynxpoint/iobp.h>
  17 #include <types.h>
  18
  19 /* Set D3Hot Power State in ACPI mode */
  20 static void serialio_enable_d3hot(struct resource *res)
  21 {
  22         u32 reg32 = read32(res2mmio(res, PCH_PCS, 0));
  23         reg32 |= PCH_PCS_PS_D3HOT;
  24         write32(res2mmio(res, PCH_PCS, 0), reg32);
  25 }
  26
  27 static bool serialio_uart_is_debug(struct device *dev)
  28 {
  29         if (CONFIG(SERIALIO_UART_CONSOLE)) {
  30                 switch (dev->path.pci.devfn) {
  31                 case PCH_DEVFN_UART0:
  32                         return CONFIG_UART_FOR_CONSOLE == 0;
  33                 case PCH_DEVFN_UART1:
  34                         return CONFIG_UART_FOR_CONSOLE == 1;
  35                 }
  36         }
  37         return false;
  38 }
  39
  40 /* Enable clock in PCI mode */
  41 static void serialio_enable_clock(struct resource *bar0)
  42 {
  43         u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0));
  44         reg32 |= SIO_REG_PPR_CLOCK_EN;
  45         write32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0), reg32);
  46 }
  47
  48 /* Put Serial IO D21:F0-F6 device into desired mode. */
  49 static void serialio_d21_mode(int sio_index, int int_pin, int acpi_mode)
  50 {
  51         u32 portctrl = SIO_IOBP_PORTCTRL_PM_CAP_PRSNT;
  52
  53         /* Snoop select 1. */
  54         portctrl |= SIO_IOBP_PORTCTRL_SNOOP_SELECT(1);
  55
  56         /* Set interrupt pin. */
  57         portctrl |= SIO_IOBP_PORTCTRL_INT_PIN(int_pin);
  58
  59         if (acpi_mode) {
  60                 /* Enable ACPI interrupt mode. */
  61                 portctrl |= SIO_IOBP_PORTCTRL_ACPI_IRQ_EN;
  62
  63                 /* Disable PCI config space. */
  64                 portctrl |= SIO_IOBP_PORTCTRL_PCI_CONF_DIS;
  65         }
  66
  67         pch_iobp_update(SIO_IOBP_PORTCTRLX(sio_index), 0, portctrl);
  68 }
  69
  70 /* Put Serial IO D23:F0 device into desired mode. */
  71 static void serialio_d23_mode(int acpi_mode)
  72 {
  73         u32 portctrl = 0;
  74
  75         /* Snoop select 1. */
  76         pch_iobp_update(SIO_IOBP_PORTCTRL1, 0,
  77                         SIO_IOBP_PORTCTRL1_SNOOP_SELECT(1));
  78
  79         if (acpi_mode) {
  80                 /* Enable ACPI interrupt mode. */
  81                 portctrl |= SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN;
  82
  83                 /* Disable PCI config space. */
  84                 portctrl |= SIO_IOBP_PORTCTRL0_PCI_CONF_DIS;
  85         }
  86
  87         pch_iobp_update(SIO_IOBP_PORTCTRL0, 0, portctrl);
  88 }
  89
  90 /* Enable LTR Auto Mode for D21:F1-F6. */
  91 static void serialio_d21_ltr(struct resource *bar0)
  92 {
  93         u32 reg;
  94
  95         /* 1. Program BAR0 + 808h[2] = 0b */
  96         reg = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
  97         reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK;
  98         write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg);
  99
 100         /* 2. Program BAR0 + 804h[1:0] = 00b */
 101         reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
 102         reg &= ~SIO_REG_PPR_RST_ASSERT;
 103         write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
 104
 105         /* 3. Program BAR0 + 804h[1:0] = 11b */
 106         reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
 107         reg |= SIO_REG_PPR_RST_ASSERT;
 108         write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
 109
 110         /* 4. Program BAR0 + 814h[31:0] = 00000000h */
 111         write32(res2mmio(bar0, SIO_REG_AUTO_LTR, 0), 0);
 112 }
 113
 114 /* Enable LTR Auto Mode for D23:F0. */
 115 static void serialio_d23_ltr(struct resource *bar0)
 116 {
 117         u32 reg;
 118
 119         /* Program BAR0 + 1008h[2] = 1b */
 120         reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0));
 121         reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK;
 122         write32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0), reg);
 123
 124         /* Program BAR0 + 1010h = 0x00000000 */
 125         write32(res2mmio(bar0, SIO_REG_SDIO_PPR_SW_LTR, 0), 0);
 126
 127         /* Program BAR0 + 3Ch[30] = 1b */
 128         reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0));
 129         reg |= SIO_REG_SDIO_PPR_CMD12_B30;
 130         write32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0), reg);
 131 }
 132
 133 /* Select I2C voltage of 1.8V or 3.3V. */
 134 static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage)
 135 {
 136         u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
 137         reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK;
 138         reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage);
 139         write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg32);
 140 }
 141
 142 /* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */
 143 static void serialio_init_once(int acpi_mode)
 144 {
 145         if (acpi_mode) {
 146                 /* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA. */
 147                 RCBA32_OR(ACPIIRQEN, (1 << 13)|(1 << 7)|(1 << 6)|(1 << 5));
 148         }
 149
 150         /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b. */
 151         pch_iobp_update(SIO_IOBP_GPIODF, ~0x0000131f, 0x0000131f);
 152
 153         /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */
 154         pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f);
 155 }
 156
 157 static void serialio_init(struct device *dev)
 158 {
 159         const struct soc_intel_broadwell_pch_config *config = config_of(dev);
 160         struct resource *bar0, *bar1;
 161         int sio_index = -1;
 162
 163         printk(BIOS_DEBUG, "Initializing Serial IO device\n");
 164
 165         /* Ensure memory and bus master are enabled */
 166         pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 167
 168         /* Find BAR0 and BAR1 */
 169         bar0 = probe_resource(dev, PCI_BASE_ADDRESS_0);
 170         if (!bar0)
 171                 return;
 172         bar1 = probe_resource(dev, PCI_BASE_ADDRESS_1);
 173         if (!bar1)
 174                 return;
 175
 176         if (!config->sio_acpi_mode)
 177                 serialio_enable_clock(bar0);
 178
 179         switch (dev->path.pci.devfn) {
 180         case PCH_DEVFN_SDMA: /* SDMA */
 181                 sio_index = SIO_ID_SDMA;
 182                 serialio_init_once(config->sio_acpi_mode);
 183                 serialio_d21_mode(sio_index, SIO_PIN_INTB,
 184                                   config->sio_acpi_mode);
 185                 break;
 186         case PCH_DEVFN_I2C0: /* I2C0 */
 187                 sio_index = SIO_ID_I2C0;
 188                 serialio_d21_ltr(bar0);
 189                 serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage);
 190                 serialio_d21_mode(sio_index, SIO_PIN_INTC,
 191                                   config->sio_acpi_mode);
 192                 break;
 193         case PCH_DEVFN_I2C1: /* I2C1 */
 194                 sio_index = SIO_ID_I2C1;
 195                 serialio_d21_ltr(bar0);
 196                 serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage);
 197                 serialio_d21_mode(sio_index, SIO_PIN_INTC,
 198                                   config->sio_acpi_mode);
 199                 break;
 200         case PCH_DEVFN_SPI0: /* SPI0 */
 201                 sio_index = SIO_ID_SPI0;
 202                 serialio_d21_ltr(bar0);
 203                 serialio_d21_mode(sio_index, SIO_PIN_INTC,
 204                                   config->sio_acpi_mode);
 205                 break;
 206         case PCH_DEVFN_SPI1: /* SPI1 */
 207                 sio_index = SIO_ID_SPI1;
 208                 serialio_d21_ltr(bar0);
 209                 serialio_d21_mode(sio_index, SIO_PIN_INTC,
 210                                   config->sio_acpi_mode);
 211                 break;
 212         case PCH_DEVFN_UART0: /* UART0 */
 213                 sio_index = SIO_ID_UART0;
 214                 if (!serialio_uart_is_debug(dev))
 215                         serialio_d21_ltr(bar0);
 216                 serialio_d21_mode(sio_index, SIO_PIN_INTD,
 217                                   config->sio_acpi_mode);
 218                 break;
 219         case PCH_DEVFN_UART1: /* UART1 */
 220                 sio_index = SIO_ID_UART1;
 221                 if (!serialio_uart_is_debug(dev))
 222                         serialio_d21_ltr(bar0);
 223                 serialio_d21_mode(sio_index, SIO_PIN_INTD,
 224                                   config->sio_acpi_mode);
 225                 break;
 226         case PCH_DEVFN_SDIO: /* SDIO */
 227                 sio_index = SIO_ID_SDIO;
 228                 serialio_d23_ltr(bar0);
 229                 serialio_d23_mode(config->sio_acpi_mode);
 230                 break;
 231         default:
 232                 return;
 233         }
 234
 235         if (config->sio_acpi_mode) {
 236                 struct device_nvs *dev_nvs = acpi_get_device_nvs();
 237
 238                 /* Save BAR0 and BAR1 to ACPI NVS */
 239                 dev_nvs->bar0[sio_index] = (u32)bar0->base;
 240                 dev_nvs->bar1[sio_index] = (u32)bar1->base;
 241
 242                 if (!serialio_uart_is_debug(dev)) {
 243                         /* Do not enable UART if it is used as debug port */
 244                         dev_nvs->enable[sio_index] = 1;
 245
 246                         /* Put device in D3hot state via BAR1 */
 247                         if (dev->path.pci.devfn != PCH_DEVFN_SDMA)
 248                                 serialio_enable_d3hot(bar1); /* all but SDMA */
 249                 }
 250         }
 251 }
 252
 253 static void serialio_read_resources(struct device *dev)
 254 {
 255         pci_dev_read_resources(dev);
 256
 257         /* Set the configured UART base address for the debug port */
 258         if (CONFIG(SERIALIO_UART_CONSOLE) && serialio_uart_is_debug(dev)) {
 259                 struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
 260                 res->base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
 261                 res->size = 0x1000;
 262                 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 263         }
 264 }
 265
 266 static struct device_operations device_ops = {
 267         .read_resources         = &serialio_read_resources,
 268         .set_resources          = &pci_dev_set_resources,
 269         .enable_resources       = &pci_dev_enable_resources,
 270         .init                   = &serialio_init,
 271         .ops_pci                = &pci_dev_ops_pci,
 272 };
 273
 274 static const unsigned short pci_device_ids[] = {
 275         0x9c60, 0x9ce0, /* 0:15.0 - SDMA */
 276         0x9c61, 0x9ce1, /* 0:15.1 - I2C0 */
 277         0x9c62, 0x9ce2, /* 0:15.2 - I2C1 */
 278         0x9c65, 0x9ce5, /* 0:15.3 - SPI0 */
 279         0x9c66, 0x9ce6, /* 0:15.4 - SPI1 */
 280         0x9c63, 0x9ce3, /* 0:15.5 - UART0 */
 281         0x9c64, 0x9ce4, /* 0:15.6 - UART1 */
 282         0x9c35, 0x9cb5, /* 0:17.0 - SDIO */
 283         0
 284 };
 285
 286 static const struct pci_driver pch_pcie __pci_driver = {
 287         .ops     = &device_ops,
 288         .vendor  = PCI_VID_INTEL,
 289         .devices = pci_device_ids,
 290 };