src/soc/intel/broadwell/pch/smi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <device/pci.h>
   5 #include <console/console.h>
   6 #include <arch/io.h>
   7 #include <cpu/x86/smm.h>
   8 #include <cpu/intel/smm_reloc.h>
   9 #include <soc/iomap.h>
  10 #include <soc/pch.h>
  11 #include <soc/pm.h>
  12
  13 void smm_southbridge_clear_state(void)
  14 {
  15         u32 smi_en;
  16
  17         smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
  18         if (smi_en & APMC_EN) {
  19                 printk(BIOS_INFO, "SMI# handler already enabled?\n");
  20                 return;
  21         }
  22
  23         /* Dump and clear status registers */
  24         clear_smi_status();
  25         clear_pm1_status();
  26         clear_tco_status();
  27         clear_gpe_status();
  28 }
  29
  30 static void smm_southbridge_enable(uint16_t pm1_events)
  31 {
  32         printk(BIOS_DEBUG, "Enabling SMIs.\n");
  33         /* Configure events */
  34         enable_pm1(pm1_events);
  35         disable_gpe(PME_B0_EN);
  36
  37         /* Enable SMI generation:
  38          *  - on APMC writes (io 0xb2)
  39          *  - on writes to SLP_EN (sleep states)
  40          *  - on writes to GBL_RLS (bios commands)
  41          * No SMIs:
  42          *  - on microcontroller writes (io 0x62/0x66)
  43          *  - on TCO events
  44          */
  45         enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
  46 }
  47
  48 void global_smi_enable(void)
  49 {
  50         smm_southbridge_enable(PWRBTN_EN | GBL_EN);
  51 }