src/soc/intel/cannonlake/Kconfig

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 config SOC_INTEL_CANNONLAKE_BASE
   4         bool
   5         select ACPI_INTEL_HARDWARE_SLEEP_VALUES
   6         select ACPI_NHLT
   7         select ARCH_X86
   8         select BOOT_DEVICE_SUPPORTS_WRITES
   9         select CACHE_MRC_SETTINGS
  10         select CPU_INTEL_COMMON
  11         select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
  12         select CPU_SUPPORTS_PM_TIMER_EMULATION
  13         select DISPLAY_FSP_VERSION_INFO
  14         select DRIVERS_USB_ACPI
  15         select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
  16         select FSP_COMPRESS_FSP_S_LZMA
  17         select FSP_M_XIP
  18         select FSP_USES_CB_STACK
  19         select GENERIC_GPIO_LIB
  20         select HAVE_DPTF_EISA_HID
  21         select HAVE_FSP_GOP
  22         select HAVE_FSP_LOGO_SUPPORT
  23         select HAVE_HYPERTHREADING
  24         select HAVE_INTEL_FSP_REPO
  25         select HAVE_SMI_HANDLER
  26         select IDT_IN_EVERY_STAGE
  27         select INTEL_DESCRIPTOR_MODE_CAPABLE
  28         select INTEL_GMA_ACPI
  29         select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
  30         select MRC_SETTINGS_PROTECT
  31         select PARALLEL_MP_AP_WORK
  32         select PLATFORM_USES_FSP2_0
  33         select PMC_GLOBAL_RESET_ENABLE_LOCK
  34         select SOC_INTEL_COMMON
  35         select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
  36         select SOC_INTEL_COMMON_BLOCK
  37         select SOC_INTEL_COMMON_BLOCK_ACPI
  38         select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
  39         select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
  40         select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
  41         select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
  42         select SOC_INTEL_COMMON_BLOCK_CAR
  43         select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
  44         select SOC_INTEL_COMMON_BLOCK_CNVI
  45         select SOC_INTEL_COMMON_BLOCK_CPU
  46         select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
  47         select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
  48         select SOC_INTEL_COMMON_BLOCK_DTT
  49         select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
  50         select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
  51         select SOC_INTEL_COMMON_BLOCK_HDA
  52         select SOC_INTEL_COMMON_BLOCK_IRQ
  53         select SOC_INTEL_COMMON_BLOCK_ME_SPEC_12
  54         select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
  55         select SOC_INTEL_COMMON_BLOCK_SA
  56         select SOC_INTEL_COMMON_BLOCK_SCS
  57         select SOC_INTEL_COMMON_BLOCK_SMM
  58         select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
  59         select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV
  60         select SOC_INTEL_COMMON_BLOCK_XHCI
  61         select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
  62         select SOC_INTEL_COMMON_FSP_RESET
  63         select SOC_INTEL_COMMON_NHLT
  64         select SOC_INTEL_COMMON_PCH_CLIENT
  65         select SOC_INTEL_COMMON_RESET
  66         select SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION
  67         select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
  68         select SSE2
  69         select SUPPORT_CPU_UCODE_IN_CBFS
  70         select TSC_MONOTONIC_TIMER
  71         select UDELAY_TSC
  72         select UDK_2017_BINDING
  73         select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
  74         select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
  75         select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
  76         select X86_CLFLUSH_CAR
  77
  78 config SOC_INTEL_COFFEELAKE
  79         bool
  80         select SOC_INTEL_CANNONLAKE_BASE
  81         select HAVE_X86_64_SUPPORT
  82         select HECI_DISABLE_USING_SMM
  83         select INTEL_CAR_NEM
  84
  85 config SOC_INTEL_WHISKEYLAKE
  86         bool
  87         select SOC_INTEL_CANNONLAKE_BASE
  88         select HECI_DISABLE_USING_SMM
  89         select INTEL_CAR_NEM_ENHANCED
  90
  91 config SOC_INTEL_COMETLAKE
  92         bool
  93         select SOC_INTEL_CANNONLAKE_BASE
  94         select INTEL_CAR_NEM_ENHANCED
  95         select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT
  96         select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
  97         select SOC_INTEL_COMMON_BASECODE
  98         select SOC_INTEL_COMMON_BASECODE_RAMTOP
  99
 100 config SOC_INTEL_COMETLAKE_1
 101         bool
 102         select SOC_INTEL_COMETLAKE
 103
 104 config SOC_INTEL_COMETLAKE_2
 105         bool
 106         select SOC_INTEL_COMETLAKE
 107
 108 config SOC_INTEL_COMETLAKE_1_2
 109         bool
 110         select SOC_INTEL_COMETLAKE
 111         select PLATFORM_USES_SECOND_FSP
 112         help
 113           Support both CML v1 and v2, for boards that may have either stepping.
 114           Embeds both FSPs and selects the correct one at runtime.  The second
 115           FSP consumes about 800 KiB of flash space.
 116
 117           The first FSP is for CML v1, the second is for CML v2.
 118
 119 config SOC_INTEL_COMETLAKE_S
 120         bool
 121         select SOC_INTEL_COMETLAKE
 122
 123 config SOC_INTEL_COMETLAKE_V
 124         bool
 125         select SOC_INTEL_COMETLAKE
 126
 127 config SOC_INTEL_CANNONLAKE_PCH_H
 128         bool
 129
 130 if SOC_INTEL_CANNONLAKE_BASE
 131
 132 config MAX_CPUS
 133         int
 134         default 20 if SOC_INTEL_CANNONLAKE_PCH_H && SOC_INTEL_COMETLAKE
 135         default 16 if SOC_INTEL_CANNONLAKE_PCH_H && SOC_INTEL_COFFEELAKE
 136         default 12 if !SOC_INTEL_CANNONLAKE_PCH_H && SOC_INTEL_COMETLAKE
 137         default 8
 138
 139 config DIMM_SPD_SIZE
 140         default 512
 141
 142 config DCACHE_RAM_BASE
 143         default 0xfef00000
 144
 145 config DCACHE_RAM_SIZE
 146         default 0x40000
 147         help
 148           The size of the cache-as-ram region required during bootblock
 149           and/or romstage.
 150
 151 config DCACHE_BSP_STACK_SIZE
 152         hex
 153         default 0x20400 if FSP_USES_CB_STACK
 154         default 0x4000
 155         help
 156           The amount of anticipated stack usage in CAR by bootblock and
 157           other stages. In the case of FSP_USES_CB_STACK default value will be
 158           sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB).
 159
 160 config FSP_TEMP_RAM_SIZE
 161         hex
 162         depends on FSP_USES_CB_STACK
 163         default 0x10000
 164         help
 165           The amount of anticipated heap usage in CAR by FSP.
 166           Refer to Platform FSP integration guide document to know
 167           the exact FSP requirement for Heap setup.
 168
 169 config CHIPSET_DEVICETREE
 170         string
 171         default "soc/intel/cannonlake/chipset_pch_h.cb" if SOC_INTEL_CANNONLAKE_PCH_H
 172         default "soc/intel/cannonlake/chipset.cb"
 173
 174 config IFD_CHIPSET
 175         string
 176         default "cnl"
 177
 178 config IED_REGION_SIZE
 179         hex
 180         default 0x400000
 181
 182 config NHLT_DMIC_1CH_16B
 183         bool
 184         depends on ACPI_NHLT
 185         default n
 186         help
 187           Include DSP firmware settings for 1 channel 16B DMIC array.
 188
 189 config NHLT_DMIC_2CH_16B
 190         bool
 191         depends on ACPI_NHLT
 192         default n
 193         help
 194           Include DSP firmware settings for 2 channel 16B DMIC array.
 195
 196 config NHLT_DMIC_4CH_16B
 197         bool
 198         depends on ACPI_NHLT
 199         default n
 200         help
 201           Include DSP firmware settings for 4 channel 16B DMIC array.
 202
 203 config NHLT_MAX98357
 204         bool
 205         depends on ACPI_NHLT
 206         default n
 207         help
 208           Include DSP firmware settings for headset codec.
 209
 210 config NHLT_MAX98373
 211         bool
 212         depends on ACPI_NHLT
 213         default n
 214         help
 215           Include DSP firmware settings for headset codec.
 216
 217 config NHLT_DA7219
 218         bool
 219         depends on ACPI_NHLT
 220         default n
 221         help
 222           Include DSP firmware settings for headset codec.
 223
 224 config MAX_ROOT_PORTS
 225         int
 226         default 24 if SOC_INTEL_CANNONLAKE_PCH_H
 227         default 16
 228
 229 config MAX_PCIE_CLOCK_SRC
 230         int
 231         default 16 if SOC_INTEL_CANNONLAKE_PCH_H
 232         default 6
 233
 234 config SMM_TSEG_SIZE
 235         hex
 236         default 0x800000
 237
 238 config SMM_RESERVED_SIZE
 239         hex
 240         default 0x200000
 241
 242 config PCR_BASE_ADDRESS
 243         hex
 244         default 0xfd000000
 245         help
 246           This option allows you to select MMIO Base Address of sideband bus.
 247
 248 config CPU_BCLK_MHZ
 249         int
 250         default 100
 251
 252 config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 253         int
 254         default 120
 255
 256 config CPU_XTAL_HZ
 257         default 24000000
 258
 259 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 260         int
 261         default 216
 262
 263 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 264         int
 265         default 3
 266
 267 config SOC_INTEL_I2C_DEV_MAX
 268         int
 269         default 4 if SOC_INTEL_CANNONLAKE_PCH_H
 270         default 6
 271
 272 config CONSOLE_UART_BASE_ADDRESS
 273         hex
 274         default 0xfe032000
 275         depends on INTEL_LPSS_UART_FOR_CONSOLE
 276
 277 # Clock divider parameters for 115200 baud rate
 278 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
 279         hex
 280         default 0x30
 281
 282 config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 283         hex
 284         default 0xc35
 285
 286 config VBOOT
 287         select VBOOT_MUST_REQUEST_DISPLAY
 288         select VBOOT_STARTS_IN_BOOTBLOCK
 289         select VBOOT_VBNV_CMOS
 290         select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
 291
 292 config CBFS_SIZE
 293         default 0x200000
 294
 295 config MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
 296         bool
 297         default n
 298         help
 299           Select this if the board has a SD_PWR_ENABLE pin connected to a
 300           active high sensing load switch to turn on power to the card reader.
 301           This will enable a workaround in ASL _PS3 and _PS0 methods to force
 302           SD_PWR_ENABLE to stay low in D3.
 303
 304 config FSP_HEADER_PATH
 305         default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
 306         default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE_1
 307         # CML v1/v2 headers are equivalent (differ only in comments) so build
 308         # against v2 arbitrarily.
 309         default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Include/" if SOC_INTEL_COMETLAKE_2 || SOC_INTEL_COMETLAKE_1_2
 310         default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/" if SOC_INTEL_COMETLAKE_S
 311         default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeV/Include/" if SOC_INTEL_COMETLAKE_V
 312
 313 config FSP_FD_PATH
 314         default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
 315         default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Fsp.fd" if SOC_INTEL_COMETLAKE_1 || SOC_INTEL_COMETLAKE_1_2
 316         default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Fsp.fd" if SOC_INTEL_COMETLAKE_2
 317         default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Fsp.fd" if SOC_INTEL_COMETLAKE_S
 318         default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeV/Fsp.fd" if SOC_INTEL_COMETLAKE_V
 319
 320 config FSP_FD_PATH_2
 321         default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Fsp.fd" if SOC_INTEL_COMETLAKE_1_2
 322
 323 config PRERAM_CBMEM_CONSOLE_SIZE
 324         hex
 325         default 0xe00
 326
 327 config INTEL_TXT_BIOSACM_ALIGNMENT
 328         hex
 329         default 0x40000 # 256KB
 330
 331 config INTEL_GMA_BCLV_OFFSET
 332         default 0xc8258
 333
 334 config INTEL_GMA_BCLV_WIDTH
 335         default 32
 336
 337 config INTEL_GMA_BCLM_OFFSET
 338         default 0xc8254
 339
 340 config INTEL_GMA_BCLM_WIDTH
 341         default 32
 342
 343 endif