src/soc/intel/cannonlake/Makefile.mk

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2 ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_BASE),y)
   3
   4 subdirs-y += romstage
   5 subdirs-y += ../../../cpu/intel/microcode
   6 subdirs-y += ../../../cpu/intel/turbo
   7 subdirs-y += ../../../cpu/intel/common
   8
   9 bootblock-y += bootblock/bootblock.c
  10 bootblock-y += bootblock/pch.c
  11 bootblock-y += pmutil.c
  12 bootblock-y += bootblock/report_platform.c
  13 bootblock-y += gspi.c
  14 bootblock-y += i2c.c
  15 bootblock-y += spi.c
  16 bootblock-y += lpc.c
  17 bootblock-y += p2sb.c
  18 bootblock-y += uart.c
  19
  20 romstage-y += cnl_memcfg_init.c
  21 romstage-y += gspi.c
  22 romstage-y += i2c.c
  23 romstage-y += lpc.c
  24 romstage-y += pmutil.c
  25 romstage-y += reset.c
  26 romstage-y += spi.c
  27 romstage-y += uart.c
  28
  29 ramstage-y += acpi.c
  30 ramstage-y += chip.c
  31 ramstage-y += cpu.c
  32 ramstage-y += elog.c
  33 ramstage-y += finalize.c
  34 ramstage-y += fsp_params.c
  35 ramstage-y += graphics.c
  36 ramstage-y += gspi.c
  37 ramstage-y += i2c.c
  38 ramstage-y += lockdown.c
  39 ramstage-y += lpc.c
  40 ramstage-y += nhlt.c
  41 ramstage-y += p2sb.c
  42 ramstage-y += pmc.c
  43 ramstage-y += pmutil.c
  44 ramstage-y += reset.c
  45 ramstage-y += spi.c
  46 ramstage-y += systemagent.c
  47 ramstage-y += uart.c
  48 ramstage-y += vr_config.c
  49 ramstage-y += sd.c
  50 ramstage-y += xhci.c
  51
  52 smm-y += elog.c
  53 smm-y += p2sb.c
  54 smm-y += pmutil.c
  55 smm-y += smihandler.c
  56 smm-y += uart.c
  57 smm-y += xhci.c
  58
  59 postcar-y += pmutil.c
  60 postcar-y += i2c.c
  61 postcar-y += gspi.c
  62 postcar-y += spi.c
  63 postcar-y += uart.c
  64
  65 verstage-y += gspi.c
  66 verstage-y += i2c.c
  67 verstage-y += pmutil.c
  68 verstage-y += spi.c
  69 verstage-y += uart.c
  70
  71 ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y)
  72 bootblock-y += gpio_cnp_h.c
  73 romstage-y += gpio_cnp_h.c
  74 ramstage-y += gpio_cnp_h.c
  75 smm-y += gpio_cnp_h.c
  76 verstage-y += gpio_cnp_h.c
  77 else
  78 bootblock-y += gpio.c
  79 romstage-y += gpio.c
  80 ramstage-y += gpio.c
  81 smm-y += gpio.c
  82 verstage-y += gpio.c
  83 endif
  84
  85 bootblock-y += gpio_common.c
  86 ramstage-y += gpio_common.c
  87
  88 romstage-$(CONFIG_SOC_INTEL_COMETLAKE_1_2) += cometlake_1_2.c
  89 ramstage-$(CONFIG_SOC_INTEL_COMETLAKE_1_2) += cometlake_1_2.c
  90
  91 ifeq ($(CONFIG_SOC_INTEL_COFFEELAKE),y)
  92 ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y)
  93 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0a
  94 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0b
  95 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0c
  96 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0d
  97 else
  98 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0a
  99 endif
 100 else ifeq ($(CONFIG_SOC_INTEL_WHISKEYLAKE),y)
 101 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0b
 102 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0c
 103 else ifeq ($(CONFIG_SOC_INTEL_COMETLAKE),y)
 104 ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y)
 105 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-a5-02
 106 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-a5-03
 107 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-a5-05
 108 else
 109 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0c
 110 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-a6-00
 111 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-a6-01
 112 endif
 113 endif
 114
 115 CPPFLAGS_common += -I$(src)/soc/intel/cannonlake
 116 CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include
 117
 118 # DSP firmware settings files.
 119 NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/cnl/nhlt-blobs
 120 DMIC_1CH_48KHZ_16B = dmic-1ch-48khz-16b.bin
 121 DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin
 122 DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin
 123 MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin
 124 DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin
 125 MAX98373_RENDER_24B = max98373-render-2ch-48khz-24b.bin
 126 MAX98373_RENDER_16B = max98373-render-2ch-48khz-16b.bin
 127
 128 cbfs-files-$(CONFIG_NHLT_DMIC_1CH_16B) += $(DMIC_1CH_48KHZ_16B)
 129 $(DMIC_1CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_1CH_48KHZ_16B)
 130 $(DMIC_1CH_48KHZ_16B)-type := raw
 131
 132 cbfs-files-$(CONFIG_NHLT_DMIC_2CH_16B) += $(DMIC_2CH_48KHZ_16B)
 133 $(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B)
 134 $(DMIC_2CH_48KHZ_16B)-type := raw
 135
 136 cbfs-files-$(CONFIG_NHLT_DMIC_4CH_16B) += $(DMIC_4CH_48KHZ_16B)
 137 $(DMIC_4CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_16B)
 138 $(DMIC_4CH_48KHZ_16B)-type := raw
 139
 140 cbfs-files-$(CONFIG_NHLT_MAX98357) += $(MAX98357_RENDER)
 141 $(MAX98357_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98357_RENDER)
 142 $(MAX98357_RENDER)-type := raw
 143
 144 cbfs-files-$(CONFIG_NHLT_MAX98373) += $(MAX98373_RENDER_16B)
 145 $(MAX98373_RENDER_16B)-file := $(NHLT_BLOB_PATH)/$(MAX98373_RENDER_16B)
 146 $(MAX98373_RENDER_16B)-type := raw
 147
 148 cbfs-files-$(CONFIG_NHLT_MAX98373) += $(MAX98373_RENDER_24B)
 149 $(MAX98373_RENDER_24B)-file := $(NHLT_BLOB_PATH)/$(MAX98373_RENDER_24B)
 150 $(MAX98373_RENDER_24B)-type := raw
 151
 152 cbfs-files-$(CONFIG_NHLT_DA7219) += $(DA7219_RENDER_CAPTURE)
 153 $(DA7219_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(DA7219_RENDER_CAPTURE)
 154 $(DA7219_RENDER_CAPTURE)-type := raw
 155
 156 endif