src/soc/intel/cannonlake/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <gpio.h>
   4 #include <intelblocks/pcr.h>
   5 #include <soc/pcr_ids.h>
   6 #include <soc/pmc.h>
   7
   8 static const struct reset_mapping rst_map[] = {
   9         { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
  10         { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
  11         { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
  12 };
  13
  14 static const struct reset_mapping rst_map_com0[] = {
  15         { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
  16         { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
  17         { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
  18         { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
  19 };
  20
  21 /*
  22  * The GPIO driver for Cannonlake on Windows/Linux expects 32 GPIOs per pad
  23  * group, regardless of whether or not there is a physical pad for each
  24  * exposed GPIO number.
  25  *
  26  * This results in the OS having a sparse GPIO map, and devices that need
  27  * to export an ACPI GPIO must use the OS expected number.
  28  *
  29  * Not all pins are usable as GPIO and those groups do not have a pad base.
  30  *
  31  * This layout matches the Linux kernel pinctrl map for CNL-LP at:
  32  * linux/drivers/pinctrl/intel/pinctrl-cannonlake.c
  33  */
  34 static const struct pad_group cnl_community0_groups[] = {
  35         INTEL_GPP_BASE(GPP_A0, GPP_A0, ESPI_CLK_LOOPBK, 0),     /* GPP_A */
  36         INTEL_GPP_BASE(GPP_A0, GPP_B0, GSPI1_CLK_LOOPBK, 32),   /* GPP_B */
  37         INTEL_GPP_BASE(GPP_A0, GPP_G0, GPP_G7, 64),             /* GPP_G */
  38         INTEL_GPP(GPP_A0, SPI0_IO_2, SPI0_CLK_LOOPBK),          /* SPI */
  39 };
  40
  41 static const struct pad_group cnl_community1_groups[] = {
  42         INTEL_GPP_BASE(GPP_D0, GPP_D0, GSPI2_CLK_LOOPBK, 96),   /* GPP_D */
  43         INTEL_GPP_BASE(GPP_D0, GPP_F0, GPP_F23, 128),           /* GPP_F */
  44         INTEL_GPP_BASE(GPP_D0, GPP_H0, GPP_H23, 160),           /* GPP_H */
  45         INTEL_GPP_BASE(GPP_D0, CNV_BTEN, vSD3_CD_B, 192),       /* VGPIO */
  46 };
  47
  48 /* This community is not visible to the OS */
  49 static const struct pad_group cnl_community2_groups[] = {
  50         INTEL_GPP(GPD0, GPD0, DRAM_RESET_B),                    /* GPD */
  51 };
  52
  53 /* This community is not visible to the OS */
  54 static const struct pad_group cnl_community3_groups[] = {
  55         INTEL_GPP(HDA_BCLK, HDA_BCLK, I2S1_TXD),                /* AZA */
  56         INTEL_GPP(HDA_BCLK, HDACPU_SDI, TRIGGER_OUT),           /* CPU */
  57 };
  58
  59 static const struct pad_group cnl_community4_groups[] = {
  60         INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256),           /* GPP_C */
  61         INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 288),           /* GPP_E */
  62         INTEL_GPP(GPP_C0, PCH_TDO, ITP_PMODE),                  /* JTAG */
  63         INTEL_GPP(GPP_C0, EDP_BKLTEN, CL_RST_B),                /* HVMOS */
  64 };
  65
  66 static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
  67         /* GPP A, B, G, SPI */
  68         [COMM_0] = {
  69                 .port = PID_GPIOCOM0,
  70                 .first_pad = GPP_A0,
  71                 .last_pad = SPI0_CLK_LOOPBK,
  72                 .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
  73                 .pad_cfg_base = PAD_CFG_BASE,
  74                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
  75                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
  76                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
  77                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
  78                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
  79                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
  80                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
  81                 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
  82                 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
  83                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
  84                 .name = "GPP_ABG",
  85                 .acpi_path = "\\_SB.PCI0.GPIO",
  86                 .reset_map = rst_map_com0,
  87                 .num_reset_vals = ARRAY_SIZE(rst_map_com0),
  88                 .groups = cnl_community0_groups,
  89                 .num_groups = ARRAY_SIZE(cnl_community0_groups),
  90         },
  91         /* GPP D, F, H, VGPIO */
  92         [COMM_1] = {
  93                 .port = PID_GPIOCOM1,
  94                 .first_pad = GPP_D0,
  95                 .last_pad = vSD3_CD_B,
  96                 .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
  97                 .pad_cfg_base = PAD_CFG_BASE,
  98                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
  99                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 100                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 101                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
 102                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 103                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 104                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 105                 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
 106                 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
 107                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 108                 .name = "GPP_DFH",
 109                 .acpi_path = "\\_SB.PCI0.GPIO",
 110                 .reset_map = rst_map,
 111                 .num_reset_vals = ARRAY_SIZE(rst_map),
 112                 .groups = cnl_community1_groups,
 113                 .num_groups = ARRAY_SIZE(cnl_community1_groups),
 114         },
 115         /* GPD */
 116         [COMM_2] = {
 117                 .port = PID_GPIOCOM2,
 118                 .first_pad = GPD0,
 119                 .last_pad = DRAM_RESET_B,
 120                 .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
 121                 .pad_cfg_base = PAD_CFG_BASE,
 122                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 123                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 124                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 125                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
 126                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 127                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 128                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 129                 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
 130                 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
 131                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 132                 .name = "GPD",
 133                 .acpi_path = "\\_SB.PCI0.GPIO",
 134                 .reset_map = rst_map,
 135                 .num_reset_vals = ARRAY_SIZE(rst_map),
 136                 .groups = cnl_community2_groups,
 137                 .num_groups = ARRAY_SIZE(cnl_community2_groups),
 138         },
 139         /* AZA, CPU */
 140         [COMM_3] = {
 141                 .port = PID_GPIOCOM3,
 142                 .first_pad = HDA_BCLK,
 143                 .last_pad = TRIGGER_OUT,
 144                 .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
 145                 .pad_cfg_base = PAD_CFG_BASE,
 146                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 147                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 148                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 149                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
 150                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 151                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 152                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 153                 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
 154                 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
 155                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 156                 .name = "GP_AC",
 157                 .acpi_path = "\\_SB.PCI0.GPIO",
 158                 .reset_map = rst_map,
 159                 .num_reset_vals = ARRAY_SIZE(rst_map),
 160                 .groups = cnl_community3_groups,
 161                 .num_groups = ARRAY_SIZE(cnl_community3_groups),
 162         },
 163         /* GPP C, E, JTAG, HVMOS */
 164         [COMM_4] = {
 165                 .port = PID_GPIOCOM4,
 166                 .first_pad = GPP_C0,
 167                 .last_pad = CL_RST_B,
 168                 .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
 169                 .pad_cfg_base = PAD_CFG_BASE,
 170                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 171                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 172                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 173                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
 174                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 175                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 176                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 177                 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
 178                 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
 179                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 180                 .name = "GPP_CEJ",
 181                 .acpi_path = "\\_SB.PCI0.GPIO",
 182                 .reset_map = rst_map,
 183                 .num_reset_vals = ARRAY_SIZE(rst_map),
 184                 .groups = cnl_community4_groups,
 185                 .num_groups = ARRAY_SIZE(cnl_community4_groups),
 186         }
 187 };
 188
 189 const struct pad_community *soc_gpio_get_community(size_t *num_communities)
 190 {
 191         *num_communities = ARRAY_SIZE(cnl_communities);
 192         return cnl_communities;
 193 }
 194
 195 const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
 196 {
 197         static const struct pmc_to_gpio_route routes[] = {
 198                 { PMC_GPP_A, GPP_A },
 199                 { PMC_GPP_B, GPP_B },
 200                 { PMC_GPP_C, GPP_C },
 201                 { PMC_GPP_D, GPP_D },
 202                 { PMC_GPP_E, GPP_E },
 203                 { PMC_GPP_F, GPP_F },
 204                 { PMC_GPP_G, GPP_G },
 205                 { PMC_GPP_H, GPP_H },
 206                 { PMC_GPD, GPD },
 207         };
 208         *num = ARRAY_SIZE(routes);
 209         return routes;
 210 }