src/soc/intel/cannonlake/graphics.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <commonlib/helpers.h>
   4 #include <device/device.h>
   5 #include <device/mmio.h>
   6 #include <device/pci_def.h>
   7 #include <drivers/intel/gma/i915_reg.h>
   8 #include <intelblocks/graphics.h>
   9 #include <soc/ramstage.h>
  10 #include <types.h>
  11
  12 void graphics_soc_panel_init(struct device *dev)
  13 {
  14         const struct soc_intel_cannonlake_config *conf = dev->chip_info;
  15         const struct i915_gpu_panel_config *panel_cfg;
  16         const struct resource *mmio_res;
  17         void *mmio;
  18         uint32_t reg32;
  19         unsigned int pwm_period, pwm_polarity, pwm_duty;
  20
  21         if (!conf)
  22                 return;
  23
  24         panel_cfg = &conf->panel_cfg;
  25
  26         mmio_res = probe_resource(dev, PCI_BASE_ADDRESS_0);
  27         if (!mmio_res || !mmio_res->base)
  28                 return;
  29         mmio = (void *)(uintptr_t)mmio_res->base;
  30
  31         /* Panel timings */
  32
  33         reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4;
  34         reg32 |= PANEL_POWER_RESET;
  35         write32(mmio + PCH_PP_CONTROL, reg32);
  36
  37         reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16;
  38         reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff;
  39         write32(mmio + PCH_PP_ON_DELAYS, reg32);
  40
  41         reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16;
  42         reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff;
  43         write32(mmio + PCH_PP_OFF_DELAYS, reg32);
  44
  45         /* Backlight */
  46         if (panel_cfg->backlight_pwm_hz) {
  47                 pwm_polarity = panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0;
  48                 pwm_period = DIV_ROUND_CLOSEST(CONFIG_CPU_XTAL_HZ, panel_cfg->backlight_pwm_hz);
  49                 pwm_duty = DIV_ROUND_CLOSEST(pwm_period, 2); /* Start with 50 % */
  50
  51                 write32(mmio + BXT_BLC_PWM_FREQ(0), pwm_period);
  52                 write32(mmio + BXT_BLC_PWM_CTL(0),  pwm_polarity);
  53                 write32(mmio + BXT_BLC_PWM_DUTY(0), pwm_duty);
  54         }
  55 }
  56
  57 const struct i915_gpu_controller_info *
  58 intel_igd_get_controller_info(const struct device *const dev)
  59 {
  60         const struct soc_intel_cannonlake_config *const chip = dev->chip_info;
  61         return &chip->gfx;
  62 }