src/soc/intel/cannonlake/lockdown.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <intelblocks/cfg.h>
   5 #include <intelblocks/pmclib.h>
   6 #include <intelpch/lockdown.h>
   7 #include <soc/pm.h>
   8
   9 static void pmc_lock_pmsync(void)
  10 {
  11         uint8_t *pmcbase;
  12         uint32_t pmsyncreg;
  13
  14         pmcbase = pmc_mmio_regs();
  15
  16         pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
  17         pmsyncreg |= PCH2CPU_TPR_CFG_LOCK;
  18         write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
  19 }
  20
  21 static void pmc_lock_abase(void)
  22 {
  23         uint8_t *pmcbase;
  24         uint32_t reg32;
  25
  26         pmcbase = pmc_mmio_regs();
  27
  28         reg32 = read32(pmcbase + GEN_PMCON_B);
  29         reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
  30         write32(pmcbase + GEN_PMCON_B, reg32);
  31 }
  32
  33 static void pmc_lock_smi(void)
  34 {
  35         uint8_t *pmcbase;
  36         uint8_t reg8;
  37
  38         pmcbase = pmc_mmio_regs();
  39
  40         reg8 = read8(pmcbase + GEN_PMCON_B);
  41         reg8 |= SMI_LOCK;
  42         write8(pmcbase + GEN_PMCON_B, reg8);
  43 }
  44
  45 static void pmc_lockdown_cfg(int chipset_lockdown)
  46 {
  47         /* PMSYNC */
  48         pmc_lock_pmsync();
  49         /* Lock down ABASE and sleep stretching policy */
  50         pmc_lock_abase();
  51         /* Make sure payload/OS can't trigger global reset */
  52         pmc_global_reset_disable_and_lock();
  53
  54         if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
  55                 pmc_lock_smi();
  56 }
  57
  58 void soc_lockdown_config(int chipset_lockdown)
  59 {
  60         /* PMC lock down configuration */
  61         pmc_lockdown_cfg(chipset_lockdown);
  62 }