src/soc/intel/cannonlake/pmutil.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * Helper functions for dealing with power management registers
   5  * and the differences between PCH variants.
   6  */
   7
   8 #define __SIMPLE_DEVICE__
   9
  10 #include <acpi/acpi_pm.h>
  11 #include <console/console.h>
  12 #include <device/mmio.h>
  13 #include <device/device.h>
  14 #include <device/pci.h>
  15 #include <gpio.h>
  16 #include <intelblocks/pmclib.h>
  17 #include <intelblocks/rtc.h>
  18 #include <intelblocks/tco.h>
  19 #include <soc/gpe.h>
  20 #include <soc/iomap.h>
  21 #include <soc/lpc.h>
  22 #include <soc/pci_devs.h>
  23 #include <soc/pm.h>
  24 #include <soc/smbus.h>
  25 #include <security/vboot/vbnv.h>
  26 #include <static.h>
  27
  28 #include "chip.h"
  29
  30 /*
  31  * SMI
  32  */
  33
  34 const char *const *soc_smi_sts_array(size_t *a)
  35 {
  36         static const char *const smi_sts_bits[] = {
  37                 [BIOS_STS_BIT] = "BIOS",
  38                 [LEGACY_USB_STS_BIT] = "LEGACY_USB",
  39                 [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
  40                 [APM_STS_BIT] = "APM",
  41                 [SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
  42                 [PM1_STS_BIT] = "PM1",
  43                 [GPE0_STS_BIT] = "GPE0",
  44                 [GPIO_STS_BIT] = "GPI",
  45                 [MCSMI_STS_BIT] = "MCSMI",
  46                 [DEVMON_STS_BIT] = "DEVMON",
  47                 [TCO_STS_BIT] = "TCO",
  48                 [PERIODIC_STS_BIT] = "PERIODIC",
  49                 [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",
  50                 [SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
  51                 [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
  52                 [MONITOR_STS_BIT] = "MONITOR",
  53                 [SPI_SMI_STS_BIT] = "SPI",
  54                 [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",
  55                 [ESPI_SMI_STS_BIT] = "ESPI_SMI",
  56         };
  57
  58         *a = ARRAY_SIZE(smi_sts_bits);
  59         return smi_sts_bits;
  60 }
  61
  62 /*
  63  * TCO
  64  */
  65
  66 const char *const *soc_tco_sts_array(size_t *a)
  67 {
  68         static const char *const tco_sts_bits[] = {
  69                 [0] = "NMI2SMI",
  70                 [1] = "SW_TCO",
  71                 [2] = "TCO_INT",
  72                 [3] = "TIMEOUT",
  73                 [7] = "NEWCENTURY",
  74                 [8] = "BIOSWR",
  75                 [9] = "DMISCI",
  76                 [10] = "DMISMI",
  77                 [12] = "DMISERR",
  78                 [13] = "SLVSEL",
  79                 [16] = "INTRD_DET",
  80                 [17] = "SECOND_TO",
  81                 [18] = "BOOT",
  82                 [20] = "SMLINK_SLV"
  83         };
  84
  85         *a = ARRAY_SIZE(tco_sts_bits);
  86         return tco_sts_bits;
  87 }
  88
  89 /*
  90  * GPE0
  91  */
  92
  93 const char *const *soc_std_gpe_sts_array(size_t *a)
  94 {
  95         static const char *const gpe_sts_bits[] = {
  96                 [1] = "HOTPLUG",
  97                 [2] = "SWGPE",
  98                 [6] = "TCO_SCI",
  99                 [7] = "SMB_WAK",
 100                 [9] = "PCI_EXP",
 101                 [10] = "BATLOW",
 102                 [11] = "PME",
 103                 [12] = "ME",
 104                 [13] = "PME_B0",
 105                 [14] = "eSPI",
 106                 [15] = "GPIO Tier-2",
 107                 [16] = "LAN_WAKE",
 108                 [18] = "WADT"
 109         };
 110
 111         *a = ARRAY_SIZE(gpe_sts_bits);
 112         return gpe_sts_bits;
 113 }
 114
 115 void pmc_set_disb(void)
 116 {
 117         /* Set the DISB after DRAM init */
 118         uint8_t disb_val;
 119         /* Only care about bits [23:16] of register GEN_PMCON_A */
 120         uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2);
 121
 122         disb_val = read8(addr);
 123         disb_val |= (DISB >> 16);
 124
 125         /* Don't clear bits that are write-1-to-clear */
 126         disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16);
 127         write8(addr, disb_val);
 128 }
 129
 130 /*
 131  * PMC controller gets hidden from PCI bus
 132  * during FSP-Silicon init call. Hence PWRMBASE
 133  * can't be accessible using PCI configuration space
 134  * read/write.
 135  */
 136 uint8_t *pmc_mmio_regs(void)
 137 {
 138         return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
 139 }
 140
 141 uintptr_t soc_read_pmc_base(void)
 142 {
 143         return (uintptr_t)pmc_mmio_regs();
 144 }
 145
 146 uint32_t *soc_pmc_etr_addr(void)
 147 {
 148         return (uint32_t *)(soc_read_pmc_base() + ETR);
 149 }
 150
 151 static void gpe0_different_values(const struct soc_intel_cannonlake_config *config)
 152 {
 153         bool result = (config->gpe0_dw0 != config->gpe0_dw1) &&
 154                          (config->gpe0_dw0 != config->gpe0_dw2) &&
 155                          (config->gpe0_dw1 != config->gpe0_dw2);
 156
 157         assert(result);
 158 }
 159
 160 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 161 {
 162         DEVTREE_CONST struct soc_intel_cannonlake_config *config;
 163         config = config_of_soc();
 164
 165         gpe0_different_values(config);
 166
 167         /* Assign to out variable */
 168         *dw0 = config->gpe0_dw0;
 169         *dw1 = config->gpe0_dw1;
 170         *dw2 = config->gpe0_dw2;
 171 }
 172
 173 static int rtc_failed(uint32_t gen_pmcon_b)
 174 {
 175         return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
 176 }
 177
 178 int soc_get_rtc_failed(void)
 179 {
 180         const struct chipset_power_state *ps;
 181
 182         if (acpi_fetch_pm_state(&ps, PS_CLAIMER_RTC) < 0)
 183                 return 1;
 184
 185         return rtc_failed(ps->gen_pmcon_b);
 186 }
 187
 188 int vbnv_cmos_failed(void)
 189 {
 190         return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
 191 }
 192
 193 static inline int deep_s3_enabled(void)
 194 {
 195         uint32_t deep_s3_pol;
 196
 197         deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
 198         return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
 199 }
 200
 201 /* Return 0, 3, or 5 to indicate the previous sleep state. */
 202 int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
 203 {
 204         /*
 205          * Check for any power failure to determine if this a wake from
 206          * S5 because the PCH does not set the WAK_STS bit when waking
 207          * from a true G3 state.
 208          */
 209         if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)))
 210                 prev_sleep_state = ACPI_S5;
 211
 212         /*
 213          * If waking from S3 determine if deep S3 is enabled. If not,
 214          * need to check both deep sleep well and normal suspend well.
 215          * Otherwise just check deep sleep well.
 216          */
 217         if (prev_sleep_state == ACPI_S3) {
 218                 /* PWR_FLR represents deep sleep power well loss. */
 219                 uint32_t mask = PWR_FLR;
 220
 221                 /* If deep s3 isn't enabled check the suspend well too. */
 222                 if (!deep_s3_enabled())
 223                         mask |= SUS_PWR_FLR;
 224
 225                 if (ps->gen_pmcon_a & mask)
 226                         prev_sleep_state = ACPI_S5;
 227         }
 228
 229         return prev_sleep_state;
 230 }
 231
 232 void soc_fill_power_state(struct chipset_power_state *ps)
 233 {
 234         uint8_t *pmc;
 235
 236         ps->tco1_sts = tco_read_reg(TCO1_STS);
 237         ps->tco2_sts = tco_read_reg(TCO2_STS);
 238
 239         printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
 240
 241         pmc = pmc_mmio_regs();
 242         ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
 243         ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
 244         ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
 245         ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
 246         ps->hpr_cause0 = read32(pmc + HPR_CAUSE0);
 247
 248         printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
 249                 ps->gen_pmcon_a, ps->gen_pmcon_b);
 250
 251         printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
 252                 ps->gblrst_cause[0], ps->gblrst_cause[1]);
 253
 254         printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0);
 255 }
 256
 257 /* STM Support */
 258 uint16_t get_pmbase(void)
 259 {
 260         return (uint16_t)ACPI_BASE_ADDRESS;
 261 }
 262
 263 /*
 264  * Set which power state system will be after reapplying
 265  * the power (from G3 State)
 266  */
 267 void pmc_soc_set_afterg3_en(const bool on)
 268 {
 269         uint8_t reg8;
 270         uint8_t *const pmcbase = pmc_mmio_regs();
 271
 272         reg8 = read8(pmcbase + GEN_PMCON_A);
 273         if (on)
 274                 reg8 &= ~SLEEP_AFTER_POWER_FAIL;
 275         else
 276                 reg8 |= SLEEP_AFTER_POWER_FAIL;
 277         write8(pmcbase + GEN_PMCON_A, reg8);
 278 }