src/soc/intel/cannonlake/systemagent.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <delay.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ops.h>
   7 #include <intelblocks/power_limit.h>
   8 #include <intelblocks/systemagent.h>
   9 #include <soc/cpu.h>
  10 #include <soc/iomap.h>
  11 #include <soc/systemagent.h>
  12 #include <static.h>
  13 #include "chip.h"
  14
  15 /*
  16  * SoC implementation
  17  *
  18  * Add all known fixed memory ranges for Host Controller/Memory
  19  * controller.
  20  */
  21 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
  22 {
  23         static const struct sa_mmio_descriptor soc_fixed_resources[] = {
  24                 { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
  25                                 "PCIEXBAR" },
  26                 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
  27                 { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
  28                 { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
  29                 { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
  30                 { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
  31         };
  32
  33         sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
  34                         ARRAY_SIZE(soc_fixed_resources));
  35
  36         /* Add Vt-d resources if VT-d is enabled. */
  37         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
  38                 return;
  39
  40         sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
  41                         ARRAY_SIZE(soc_vtd_resources));
  42 }
  43
  44 /*
  45  * SoC implementation
  46  *
  47  * Perform System Agent Initialization during Ramstage phase.
  48  */
  49 void soc_systemagent_init(struct device *dev)
  50 {
  51         struct soc_power_limits_config *soc_config;
  52         config_t *config;
  53
  54         /* Enable Power Aware Interrupt Routing */
  55         enable_power_aware_intr();
  56
  57         /* Enable BIOS Reset CPL */
  58         enable_bios_reset_cpl();
  59
  60         /* Configure turbo power limits 1ms after reset complete bit */
  61         mdelay(1);
  62         config = config_of_soc();
  63         soc_config = &config->power_limits_config;
  64         set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
  65 }
  66
  67 uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
  68 {
  69         switch (capid0_a_ddrsz) {
  70         case 1:
  71                 return 8192;
  72         case 2:
  73                 return 4096;
  74         case 3:
  75                 return 2048;
  76         default:
  77                 return 32768;
  78         }
  79 }