src/soc/intel/common/block/lpss/lpss.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <device/pci_def.h>
   5 #include <device/pci_ops.h>
   6 #include <intelblocks/lpss.h>
   7
   8 /* Clock register */
   9 #define LPSS_CLOCK_CTL_REG      0x200
  10 #define LPSS_CNT_CLOCK_EN       1
  11 #define LPSS_CNT_CLK_UPDATE     (1 << 31)
  12 #define LPSS_CLOCK_DIV_N(n)     (((n) & 0x7fff) << 16)
  13 #define LPSS_CLOCK_DIV_M(m)     (((m) & 0x7fff) << 1)
  14
  15 /* reset register  */
  16 #define LPSS_RESET_CTL_REG      0x204
  17
  18 /*
  19  * Bit 1:0 controls LPSS controller reset.
  20  *
  21  * 00 ->LPSS Host Controller is in reset (Reset Asserted)
  22  * 01/10 ->Reserved
  23  * 11 ->LPSS Host Controller is NOT at reset (Reset Released)
  24  */
  25
  26 #define LPSS_CNT_RST_RELEASE    3
  27
  28 /* DMA Software Reset Control */
  29 #define LPSS_DMA_RST_RELEASE    (1 << 2)
  30
  31 /* Power management control and status register */
  32 #define PME_CTRL_STATUS 0x84
  33 /* Bit 1:0 Powerstate, controls D0 and D3 state */
  34 #define POWER_STATE_MASK        3
  35
  36 bool lpss_is_controller_in_reset(uintptr_t base)
  37 {
  38         uint8_t *addr = (void *)base;
  39         uint32_t val = read32(addr + LPSS_RESET_CTL_REG);
  40
  41         if (val == 0xFFFFFFFF)
  42                 return true;
  43
  44         return !(val & LPSS_CNT_RST_RELEASE);
  45 }
  46
  47 void lpss_reset_release(uintptr_t base)
  48 {
  49         uint8_t *addr = (void *)base;
  50
  51         /* Take controller out of reset */
  52         write32(addr + LPSS_RESET_CTL_REG, LPSS_CNT_RST_RELEASE);
  53 }
  54
  55 void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val)
  56 {
  57         uint8_t *addr = (void *)base;
  58         uint32_t clk_sel;
  59
  60         addr += LPSS_CLOCK_CTL_REG;
  61         clk_sel = LPSS_CLOCK_DIV_N(clk_n_val) | LPSS_CLOCK_DIV_M(clk_m_val);
  62         clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN;
  63
  64         write32(addr, clk_sel);
  65 }
  66
  67 /* Set controller power state to D0 or D3 */
  68 void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state)
  69 {
  70         uint8_t reg8 = pci_s_read_config8(devfn, PME_CTRL_STATUS);
  71         reg8 &= ~POWER_STATE_MASK;
  72         reg8 |= state;
  73         pci_s_write_config8(devfn, PME_CTRL_STATUS, reg8);
  74 }