src/soc/intel/common/block/thermal/thermal_pmc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <intelblocks/pmclib.h>
   5 #include <intelblocks/thermal.h>
   6
   7 /*
   8  * Thermal configuration has evolved over time. With older platform the
   9  * thermal device is sitting over PCI and allow to configure its configuration
  10  * register by accessing the PCI configuration space or MMIO space.
  11  *
  12  * Since Tiger Lake, thermal registers are being moved behind the PMC PCI device
  13  * hence, accessing thermal configuration registers would need making access
  14  * to PWRMBASE. In this case SoC Kconfig to select
  15  * SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC to allow thermal configuration.
  16  */
  17 void pch_thermal_configuration(void)
  18 {
  19         uintptr_t pmc_bar = soc_read_pmc_base();
  20
  21         struct pmc_thermal_config {
  22                 uint16_t offset;
  23                 uint32_t mask;
  24                 uint32_t value;
  25         } config[] = {
  26                 {
  27                         .offset = PMC_PWRM_THERMAL_CTEN,
  28                         .value = PMC_PWRM_THERMAL_CTEN_CPDEN | PMC_PWRM_THERMAL_CTEN_CTENLOCK,
  29                 },
  30                 {
  31                         .offset = PMC_PWRM_THERMAL_ECRPTEN,
  32                         .value = PMC_PWRM_THERMAL_ECRPTEN_EN_RPT
  33                                          | PMC_PWRM_THERMAL_ECRPTEN_ECRPTENLOCK,
  34                 },
  35                 {
  36                         .offset = PMC_PWRM_THERMAL_TL,
  37                         .mask = ~0,
  38                         .value = pch_get_ltt_value() | PMC_PWRM_THERMAL_TL_TTEN
  39                                          | PMC_PWRM_THERMAL_TL_TLLOCK,
  40                 },
  41                 {
  42                         .offset = PMC_PWRM_THERMAL_PHLC,
  43                         .value = PMC_PWRM_THERMAL_PHLC_PHLCLOCK,
  44                 },
  45                 {
  46                         .offset = PMC_PWRM_THERMAL_TLEN,
  47                         .value = PMC_PWRM_THERMAL_TLEN_TLENLOCK,
  48                 },
  49         };
  50
  51         for (int i = 0; i < ARRAY_SIZE(config); i++)
  52                 clrsetbits32((void *)(pmc_bar + config[i].offset), config[i].mask,
  53                                  config[i].value);
  54 }