src/soc/intel/denverton_ns/acpi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <acpi/acpi_gnvs.h>
   5 #include <acpi/acpigen.h>
   6 #include <arch/ioapic.h>
   7 #include <arch/smp/mpspec.h>
   8 #include <cpu/cpu.h>
   9 #include <cpu/x86/smm.h>
  10 #include <string.h>
  11 #include <device/pci.h>
  12 #include <device/pci_ops.h>
  13 #include <cbmem.h>
  14 #include <console/console.h>
  15 #include <intelblocks/acpi.h>
  16 #include <soc/acpi.h>
  17 #include <soc/cpu.h>
  18 #include <soc/nvs.h>
  19 #include <soc/soc_util.h>
  20 #include <soc/pmc.h>
  21 #include <soc/systemagent.h>
  22 #include <soc/pci_devs.h>
  23
  24 #define CSTATE_RES(address_space, width, offset, address)               \
  25         {                                                               \
  26         .space_id = address_space,                                      \
  27         .bit_width = width,                                             \
  28         .bit_offset = offset,                                           \
  29         .addrl = address,                                               \
  30         }
  31
  32 static const acpi_cstate_t cstate_map[] = {
  33         {
  34                 /* C1 */
  35                 .ctype = 1,             /* ACPI C1 */
  36                 .latency = 2,
  37                 .power = 1000,
  38                 .resource = MWAIT_RES(0, 0),
  39         },
  40         {
  41                 .ctype = 2,             /* ACPI C2 */
  42                 .latency = 10,
  43                 .power = 10,
  44                 .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0,
  45                                        ACPI_BASE_ADDRESS + 0x14),
  46         },
  47         {
  48                 .ctype = 3,             /* ACPI C3 */
  49                 .latency = 50,
  50                 .power = 10,
  51                 .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0,
  52                                        ACPI_BASE_ADDRESS + 0x15),
  53         }
  54 };
  55
  56 void soc_fill_gnvs(struct global_nvs *gnvs)
  57 {
  58         /* Top of Low Memory (start of resource allocation) */
  59         gnvs->tolm = cbmem_top();
  60
  61         /* MMIO Low/High & TSEG base and length */
  62         gnvs->mmiob = (u32)get_top_of_low_memory();
  63         gnvs->mmiol = (u32)(get_pciebase() - 1);
  64         gnvs->mmiohb = (u64)get_top_of_upper_memory();
  65         gnvs->mmiohl = (u64)(((u64)1 << cpu_phys_address_size()) - 1);
  66         gnvs->tsegb = (u32)get_tseg_memory();
  67         gnvs->tsegl = (u32)(get_top_of_low_memory() - get_tseg_memory());
  68 }
  69
  70 uint32_t soc_read_sci_irq_select(void)
  71 {
  72         struct device *dev = get_pmc_dev();
  73
  74         if (!dev)
  75                 return 0;
  76
  77         return pci_read_config32(dev, PMC_ACPI_CNT);
  78 }
  79
  80 const acpi_cstate_t *soc_get_cstate_map(size_t *entries)
  81 {
  82         *entries = ARRAY_SIZE(cstate_map);
  83         return cstate_map;
  84 }
  85
  86 void soc_fill_fadt(acpi_fadt_t *fadt)
  87 {
  88         u16 pmbase = get_pmbase();
  89
  90         /* Power Control */
  91         fadt->pm2_cnt_blk = pmbase + PM2_CNT;
  92         fadt->pm_tmr_blk = pmbase + PM1_TMR;
  93
  94         /* Control Registers - Length */
  95         fadt->pm2_cnt_len = 1;
  96         fadt->pm_tmr_len = 4;
  97
  98         fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
  99
 100         /* PM Extended Registers */
 101         fill_fadt_extended_pm_io(fadt);
 102 }
 103
 104 static acpi_tstate_t denverton_tss_table[] = {
 105         { 100, 1000, 0, 0x00, 0 },
 106         { 88, 875, 0, 0x1e, 0 },
 107         { 75, 750, 0, 0x1c, 0 },
 108         { 63, 625, 0, 0x1a, 0 },
 109         { 50, 500, 0, 0x18, 0 },
 110         { 38, 375, 0, 0x16, 0 },
 111         { 25, 250, 0, 0x14, 0 },
 112         { 13, 125, 0, 0x12, 0 },
 113 };
 114
 115 acpi_tstate_t *soc_get_tss_table(int *entries)
 116 {
 117         *entries = ARRAY_SIZE(denverton_tss_table);
 118         return denverton_tss_table;
 119 }
 120
 121 void soc_power_states_generation(int core_id, int cores_per_package)
 122 {
 123         generate_p_state_entries(core_id, cores_per_package);
 124
 125         generate_t_state_entries(core_id, cores_per_package);
 126 }
 127
 128 int soc_madt_sci_irq_polarity(int sci)
 129 {
 130         if (sci >= 20)
 131                 return MP_IRQ_POLARITY_LOW;
 132         else
 133                 return MP_IRQ_POLARITY_HIGH;
 134 }
 135
 136 unsigned long southcluster_write_acpi_tables(const struct device *device,
 137                                              unsigned long current,
 138                                              struct acpi_rsdp *rsdp)
 139 {
 140         acpi_header_t *ssdt2;
 141
 142         current = acpi_write_hpet(device, current, rsdp);
 143         current = (ALIGN_UP(current, 16));
 144
 145         ssdt2 = (acpi_header_t *)current;
 146         memset(ssdt2, 0, sizeof(acpi_header_t));
 147         acpi_create_serialio_ssdt(ssdt2);
 148         if (ssdt2->length) {
 149                 current += ssdt2->length;
 150                 acpi_add_table(rsdp, ssdt2);
 151                 printk(BIOS_DEBUG, "ACPI:     * SSDT2 @ %p Length %x\n", ssdt2,
 152                        ssdt2->length);
 153                 current = (ALIGN_UP(current, 16));
 154         } else {
 155                 ssdt2 = NULL;
 156                 printk(BIOS_DEBUG, "ACPI:     * SSDT2 not generated.\n");
 157         }
 158
 159         printk(BIOS_DEBUG, "current = %lx\n", current);
 160
 161         return current;
 162 }
 163
 164 __weak void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {}
 165
 166 static unsigned long acpi_fill_dmar(unsigned long current)
 167 {
 168         uint64_t vtbar;
 169         unsigned long tmp = current;
 170
 171         vtbar = read64((void *)(DEFAULT_MCHBAR + MCH_VTBAR_OFFSET)) & MCH_VTBAR_MASK;
 172         printk(BIOS_DEBUG, "DEFVTBAR:0x%llx\n", vtbar);
 173         if (!vtbar)
 174                 return current;
 175
 176         current += acpi_create_dmar_drhd_4k(current,
 177                         DRHD_INCLUDE_PCI_ALL, 0, vtbar);
 178
 179         current += acpi_create_dmar_ds_ioapic_from_hw(current,
 180                         IO_APIC_ADDR, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);
 181         current += acpi_create_dmar_ds_msi_hpet(current,
 182                         0, PCH_HPET_PCI_BUS, PCH_HPET_PCI_SLOT, 0);
 183
 184         acpi_dmar_drhd_fixup(tmp, current);
 185
 186         /* Create RMRR; see "VTD PLATFORM CONFIGURATION" in FSP log */
 187         tmp = current;
 188         current += acpi_create_dmar_rmrr(current, 0,
 189                                          RMRR_USB_BASE_ADDRESS,
 190                                          RMRR_USB_LIMIT_ADDRESS);
 191         current += acpi_create_dmar_ds_pci(current,
 192                         0, XHCI_DEV, XHCI_FUNC);
 193         acpi_dmar_rmrr_fixup(tmp, current);
 194
 195         return current;
 196 }
 197
 198 unsigned long systemagent_write_acpi_tables(const struct device *dev,
 199                                             unsigned long current,
 200                                             struct acpi_rsdp *const rsdp)
 201 {
 202         /* Create DMAR table only if we have VT-d capability. */
 203         const u32 capid0_a = pci_read_config32(dev, CAPID0_A);
 204         if (capid0_a & VTD_DISABLE)
 205                 return current;
 206
 207         acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
 208         printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
 209         acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
 210         current += dmar->header.length;
 211         current = acpi_align_current(current);
 212         acpi_add_table(rsdp, dmar);
 213
 214         return current;
 215 }