1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <commonlib/console/post_codes.h>
4 #include <console/console.h>
5 #include <device/device.h>
6 #include <device/mmio.h>
7 #include <device/pci_ops.h>
8 #include <intelblocks/fast_spi.h>
9 #include <intelblocks/gspi.h>
10 #include <intelblocks/lpc_lib.h>
11 #include <intelblocks/p2sb.h>
12 #include <intelblocks/pcr.h>
13 #include <intelblocks/pmclib.h>
14 #include <intelblocks/rtc.h>
15 #include <intelpch/espi.h>
16 #include <soc/bootblock.h>
17 #include <soc/iomap.h>
20 #include <soc/pci_devs.h>
21 #include <soc/pcr_ids.h>
24 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x0C00
26 #define PCR_PSFX_TO_SHDW_BAR0 0
27 #define PCR_PSFX_TO_SHDW_BAR1 0x4
28 #define PCR_PSFX_TO_SHDW_BAR2 0x8
29 #define PCR_PSFX_TO_SHDW_BAR3 0xC
30 #define PCR_PSFX_TO_SHDW_BAR4 0x10
31 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
32 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C
34 static void soc_config_pwrmbase(void)
37 * Assign Resources to PWRMBASE
38 * Clear BIT 1-2 Command Register
40 pci_and_config16(PCH_DEV_PMC
, PCI_COMMAND
, ~(PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
));
42 /* Program PWRM Base */
43 pci_write_config32(PCH_DEV_PMC
, PWRMBASE
, PCH_PWRM_BASE_ADDRESS
);
45 /* Enable Bus Master and MMIO Space */
46 pci_or_config16(PCH_DEV_PMC
, PCI_COMMAND
, (PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
));
48 /* Enable PWRM in PMC */
49 setbits32((void *)PCH_PWRM_BASE_ADDRESS
+ ACTL
, PWRM_EN
);
52 void bootblock_pch_early_init(void)
55 * Perform P2SB configuration before any another controller initialization as the
56 * controller might want to perform PCR settings.
59 p2sb_configure_hpet();
61 fast_spi_early_init(SPI_BASE_ADDRESS
);
62 gspi_early_bar_init();
65 * Enabling PWRM Base for accessing
66 * Global Reset Cause Register.
68 soc_config_pwrmbase();
71 static void soc_config_acpibase(void)
73 uint32_t pmc_reg_value
;
74 const uint32_t pmc_base_reg
= PCR_PSF3_TO_SHDW_PMC_REG_BASE
;
76 pmc_reg_value
= pcr_read32(PID_PSF3
, pmc_base_reg
+ PCR_PSFX_TO_SHDW_BAR4
);
78 if (pmc_reg_value
!= 0xffffffff) {
79 /* Disable IO Space before changing the address */
80 pcr_rmw32(PID_PSF3
, pmc_base_reg
+ PCR_PSFX_T0_SHDW_PCIEN
,
81 ~PCR_PSFX_TO_SHDW_PCIEN_IOEN
, 0);
82 /* Program ABASE in PSF3 PMC space BAR4*/
83 pcr_write32(PID_PSF3
, pmc_base_reg
+ PCR_PSFX_TO_SHDW_BAR4
,
86 pcr_rmw32(PID_PSF3
, pmc_base_reg
+ PCR_PSFX_T0_SHDW_PCIEN
,
87 0xffffffff, PCR_PSFX_TO_SHDW_PCIEN_IOEN
);
91 void pch_early_iorange_init(void)
93 uint16_t io_enables
= LPC_IOE_SUPERIO_2E_2F
| LPC_IOE_KBC_60_64
|
94 LPC_IOE_EC_62_66
| LPC_IOE_LGE_200
;
97 if (CONFIG(DRIVERS_UART_8250IO
))
98 lpc_io_setup_comm_a_b();
100 /* IO Decode Enable */
101 lpc_enable_fixed_io_ranges(io_enables
);
103 /* Program generic IO Decode Range */
107 void bootblock_pch_init(void)
110 * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
111 * GPE0_STS, GPE0_EN registers.
113 soc_config_acpibase();
115 /* Set up GPE configuration */
118 enable_rtc_upper_bank();