soc/mediatek/mt8196: Initialize SSPM
[coreboot.git] / src / soc / intel / elkhartlake / cpu.c
blob4e85d01840d8c48bbeb2640a135bab0eb4842fd8
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <cpu/intel/smm_reloc.h>
4 #include <cpu/intel/turbo.h>
5 #include <cpu/intel/common/common.h>
6 #include <cpu/x86/mp.h>
7 #include <cpu/x86/msr.h>
8 #include <device/pci.h>
9 #include <fsp/api.h>
10 #include <intelblocks/cpulib.h>
11 #include <intelblocks/mp_init.h>
12 #include <intelblocks/msr.h>
13 #include <soc/cpu.h>
14 #include <soc/msr.h>
15 #include <soc/pci_devs.h>
16 #include <soc/soc_chip.h>
17 #include <static.h>
18 #include <types.h>
20 bool cpu_soc_is_in_untrusted_mode(void)
22 msr_t msr;
24 msr = rdmsr(MSR_BIOS_DONE);
25 return !!(msr.lo & ENABLE_IA_UNTRUSTED);
28 void cpu_soc_bios_done(void)
30 msr_t msr;
32 msr = rdmsr(MSR_BIOS_DONE);
33 msr.lo |= ENABLE_IA_UNTRUSTED;
34 wrmsr(MSR_BIOS_DONE, msr);
37 static void soc_fsp_load(void)
39 fsps_load();
42 static void configure_misc(void)
44 msr_t msr;
46 config_t *conf = config_of_soc();
48 msr = rdmsr(IA32_MISC_ENABLE);
49 msr.lo |= (1 << 0); /* Fast String enable */
50 msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
51 wrmsr(IA32_MISC_ENABLE, msr);
53 /* Set EIST status */
54 cpu_set_eist(conf->eist_enable);
56 /* Disable Thermal interrupts */
57 msr.lo = 0;
58 msr.hi = 0;
59 wrmsr(IA32_THERM_INTERRUPT, msr);
61 /* Enable package critical interrupt only */
62 msr.lo = 1 << 4;
63 msr.hi = 0;
64 wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
66 /* Enable PROCHOT */
67 msr = rdmsr(MSR_POWER_CTL);
68 msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */
69 msr.lo |= (1 << 23); /* Lock it */
70 wrmsr(MSR_POWER_CTL, msr);
72 /* In some cases it is beneficial for the performance to disable the
73 L1 prefetcher as on Elkhart Lake it is set up a bit too aggressive. */
74 if (conf->L1_prefetcher_disable) {
75 msr = rdmsr(MSR_PREFETCH_CTL);
76 msr.lo |= PREFETCH_L1_DISABLE;
77 wrmsr(MSR_PREFETCH_CTL, msr);
81 /* All CPUs including BSP will run the following function. */
82 void soc_core_init(struct device *cpu)
84 /* Clear out pending MCEs */
85 /* TODO(adurbin): This should only be done on a cold boot. Also, some
86 * of these banks are core vs package scope. For now every CPU clears
87 * every bank. */
88 mca_configure();
90 enable_lapic_tpr();
92 /* Configure Enhanced SpeedStep and Thermal Sensors */
93 configure_misc();
95 enable_pm_timer_emulation();
97 /* Enable Direct Cache Access */
98 configure_dca_cap();
100 /* Set energy policy */
101 set_energy_perf_bias(ENERGY_POLICY_NORMAL);
103 /* Enable Turbo */
104 enable_turbo();
107 static void per_cpu_smm_trigger(void)
109 /* Relocate the SMM handler. */
110 smm_relocate();
113 static void post_mp_init(void)
115 /* Set Max Ratio */
116 cpu_set_max_ratio();
119 * Now that all APs have been relocated as well as the BSP let SMIs
120 * start flowing.
122 global_smi_enable();
125 static const struct mp_ops mp_ops = {
127 * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
128 * that are set prior to ramstage.
129 * Real MTRRs programming are being done after resource allocation.
131 .pre_mp_init = soc_fsp_load,
132 .get_cpu_count = get_cpu_count,
133 .get_smm_info = smm_info,
134 .get_microcode_info = get_microcode_info,
135 .pre_mp_smm_init = smm_initialize,
136 .per_cpu_smm_trigger = per_cpu_smm_trigger,
137 .relocation_handler = smm_relocation_handler,
138 .post_mp_init = post_mp_init,
141 void mp_init_cpus(struct bus *cpu_bus)
143 /* TODO: Handle mp_init_with_smm failure? */
144 mp_init_with_smm(cpu_bus, &mp_ops);
146 /* Thermal throttle activation offset */
147 configure_tcc_thermal_target();