src/soc/intel/elkhartlake/fsp_params.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 #include <assert.h>
   3 #include <cbfs.h>
   4 #include <console/console.h>
   5 #include <device/device.h>
   6 #include <fsp/api.h>
   7 #include <fsp/ppi/mp_service_ppi.h>
   8 #include <fsp/util.h>
   9 #include <option.h>
  10 #include <intelblocks/lpss.h>
  11 #include <intelblocks/pmclib.h>
  12 #include <intelblocks/xdci.h>
  13 #include <intelpch/lockdown.h>
  14 #include <soc/intel/common/vbt.h>
  15 #include <soc/pci_devs.h>
  16 #include <soc/ramstage.h>
  17 #include <soc/soc_chip.h>
  18 #include <static.h>
  19 #include <types.h>
  20
  21 /* SATA DEVSLP idle timeout default values */
  22 #define DEF_DMVAL               15
  23 #define DEF_DITOVAL_MS          625
  24
  25 /* Native function controls pads termination */
  26 #define GPIO_TERM_NATIVE        0x1F
  27
  28 /* PM related values */
  29 /* Imon offset is defined in 1/1000 increments */
  30 #define IMON_OFFSET     1
  31 /* Policy Imon slope is defined in 1/100 increments */
  32 #define IMON_SLOPE      100
  33 /* Thermal Design Current current limit in 1/8A units */
  34 #define TDC_CURRENT_LIMIT_MAX   112
  35 /* AcLoadline in 1/100 mOhms */
  36 #define AC_LOADLINE_LANE_0_MAX  112
  37 #define AC_LOADLINE_LANE_1_MAX  3
  38 /* DcLoadline in 1/100 mOhms */
  39 #define DC_LOADLINE_LANE_0_MAX  92
  40 #define DC_LOADLINE_LANE_1_MAX  3
  41 /* VR Icc Max limit. 0-255A in 1/4 A units */
  42 #define ICC_LIMIT_MAX   104
  43 /* Core Ratio Limit: For overclocking part: LFM to Fused */
  44 #define CORE_RATIO_LIMIT        0x13
  45
  46 /*
  47  * Chip config parameter PcieRpL1Substates uses (UPD value + 1)
  48  * because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
  49  * In order to ensure that mainboard setting does not disable L1 substates
  50  * incorrectly, chip config parameter values are offset by 1 with 0 meaning
  51  * use FSP UPD default. get_l1_substate_control() ensures that the right UPD
  52  * value is set in fsp_params.
  53  * 0: Use FSP UPD default
  54  * 1: Disable L1 substates
  55  * 2: Use L1.1
  56  * 3: Use L1.2 (FSP UPD default)
  57  */
  58 static int get_l1_substate_control(enum L1_substates_control ctl)
  59 {
  60         if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
  61                 ctl = L1_SS_L1_2;
  62         return ctl - 1;
  63 }
  64
  65 static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg,
  66                 const struct soc_intel_elkhartlake_config *config)
  67 {
  68         s_cfg->PchFivrExtV1p05RailEnabledStates = config->fivr.v1p05_state;
  69         s_cfg->PchFivrExtV1p05RailSupportedVoltageStates = config->fivr.v1p05_rail;
  70         s_cfg->PchFivrExtVnnRailEnabledStates = config->fivr.vnn_state;
  71         s_cfg->PchFivrExtVnnRailSupportedVoltageStates = config->fivr.vnn_rail;
  72         s_cfg->PchFivrExtVnnRailSxEnabledStates = config->fivr.vnn_sx_state;
  73         s_cfg->PchFivrVccinAuxLowToHighCurModeVolTranTime = config->fivr.vcc_low_high_us;
  74         s_cfg->PchFivrVccinAuxRetToHighCurModeVolTranTime = config->fivr.vcc_ret_high_us;
  75         s_cfg->PchFivrVccinAuxRetToLowCurModeVolTranTime = config->fivr.vcc_ret_low_us;
  76         s_cfg->PchFivrVccinAuxOffToHighCurModeVolTranTime = config->fivr.vcc_off_high_us;
  77         /* Convert mV to number of 2.5 mV increments */
  78         s_cfg->PchFivrExtVnnRailSxVoltage = (config->fivr.vnn_sx_mv * 10) / 25;
  79         s_cfg->PchFivrExtV1p05RailIccMaximum = config->fivr.v1p05_icc_max_ma;
  80         s_cfg->FivrSpreadSpectrum = config->fivr.spread_spectrum;
  81 }
  82
  83 static void fill_fsps_tsn_params(FSP_S_CONFIG *params,
  84                 const struct soc_intel_elkhartlake_config *config)
  85 {
  86         /*
  87          * Currently EHL TSN GBE only supports link speed with 2 type of
  88          * PCH XTAL frequency: 24 MHz and 38.4 MHz.
  89          * These are the config values for PchTsnGbeLinkSpeed in FSP-S UPD:
  90          * 0: 24MHz 2.5Gbps, 1: 24MHz 1Gbps, 2: 38.4MHz 2.5Gbps,
  91          * 3: 38.4MHz 1Gbps
  92          */
  93         int xtal_freq_enum = pmc_get_xtal_freq();
  94         if ((xtal_freq_enum != XTAL_24_MHZ) && (xtal_freq_enum != XTAL_38_4_MHZ)) {
  95                 printk(BIOS_ERR, "XTAL not supported. Disabling All TSN GBE ports.\n");
  96                 params->PchTsnEnable = 0;
  97                 params->PchPseGbeEnable[0] = 0;
  98                 params->PchPseGbeEnable[1] = 0;
  99                 devfn_disable(pci_root_bus(), PCH_DEVFN_GBE);
 100                 devfn_disable(pci_root_bus(), PCH_DEVFN_PSEGBE0);
 101                 devfn_disable(pci_root_bus(), PCH_DEVFN_PSEGBE1);
 102         }
 103         /*
 104          * PCH TSN settings:
 105          * Due to EHL GBE comes with time sensitive networking (TSN)
 106          * capability integrated, EHL FSP is using PchTsnEnable instead of
 107          * usual PchLanEnable flag for GBE control. Hence, force
 108          * PchLanEnable to disable to avoid it being used in the future.
 109          */
 110         params->PchLanEnable = 0x0;
 111         params->PchTsnEnable = is_devfn_enabled(PCH_DEVFN_GBE);
 112         if (params->PchTsnEnable) {
 113                 params->PchTsnGbeSgmiiEnable = config->PchTsnGbeSgmiiEnable;
 114                 params->PchTsnGbeMultiVcEnable = config->PchTsnGbeMultiVcEnable;
 115                 params->PchTsnGbeLinkSpeed = (config->PchTsnGbeLinkSpeed) + xtal_freq_enum;
 116         }
 117
 118         /* PSE TSN settings */
 119         if (!CONFIG(PSE_ENABLE))
 120                 return;
 121         for (unsigned int i = 0; i < MAX_PSE_TSN_PORTS; i++) {
 122                 switch (i) {
 123                 case 0:
 124                         params->PchPseGbeEnable[i] = is_devfn_enabled(PCH_DEVFN_PSEGBE0) ?
 125                                 Host_Owned : config->PseGbeOwn[0];
 126                         break;
 127                 case 1:
 128                         params->PchPseGbeEnable[i] = is_devfn_enabled(PCH_DEVFN_PSEGBE1) ?
 129                                 Host_Owned : config->PseGbeOwn[i];
 130                         break;
 131                 default:
 132                         break;
 133                 }
 134                 if (params->PchPseGbeEnable[i]) {
 135                         params->PseTsnGbeMultiVcEnable[i] = config->PseTsnGbeMultiVcEnable[i];
 136                         params->PseTsnGbeSgmiiEnable[i] = config->PseTsnGbeSgmiiEnable[i];
 137                         params->PseTsnGbePhyInterfaceType[i] =
 138                                 !config->PseTsnGbeSgmiiEnable[i] ?
 139                                 RGMII : config->PseTsnGbePhyType[i];
 140                         params->PseTsnGbeLinkSpeed[i] =
 141                                 (params->PseTsnGbePhyInterfaceType[i] < SGMII_plus) ?
 142                                 xtal_freq_enum + 1 : xtal_freq_enum;
 143                 }
 144         }
 145 }
 146
 147 static void fill_fsps_pse_params(FSP_S_CONFIG *params,
 148                 const struct soc_intel_elkhartlake_config *config)
 149 {
 150         static char psefwbuf[(CONFIG_PSE_FW_FILE_SIZE_KIB +
 151                 CONFIG_PSE_CONFIG_BUFFER_SIZE_KIB) * KiB];
 152         uint32_t pse_fw_base;
 153         size_t psefwsize = cbfs_load("pse.bin", psefwbuf, sizeof(psefwbuf));
 154         if (psefwsize > 0) {
 155                 pse_fw_base = (uintptr_t)&psefwbuf;
 156                 params->SiipRegionBase = pse_fw_base;
 157                 params->SiipRegionSize = psefwsize;
 158                 printk(BIOS_DEBUG, "PSE base: %08x size: %08zx\n", pse_fw_base, psefwsize);
 159
 160                 /* Configure PSE peripherals */
 161                 FSP_ARRAY_LOAD(params->PchPseDmaEnable, config->PseDmaOwn);
 162                 FSP_ARRAY_LOAD(params->PchPseDmaSbInterruptEnable, config->PseDmaSbIntEn);
 163                 FSP_ARRAY_LOAD(params->PchPseUartEnable, config->PseUartOwn);
 164                 FSP_ARRAY_LOAD(params->PchPseUartSbInterruptEnable, config->PseUartSbIntEn);
 165                 FSP_ARRAY_LOAD(params->PchPseHsuartEnable, config->PseHsuartOwn);
 166                 FSP_ARRAY_LOAD(params->PchPseQepEnable, config->PseQepOwn);
 167                 FSP_ARRAY_LOAD(params->PchPseQepSbInterruptEnable, config->PseQepSbIntEn);
 168                 FSP_ARRAY_LOAD(params->PchPseI2cEnable, config->PseI2cOwn);
 169                 FSP_ARRAY_LOAD(params->PchPseI2cSbInterruptEnable, config->PseI2cSbIntEn);
 170                 FSP_ARRAY_LOAD(params->PchPseI2sEnable, config->PseI2sOwn);
 171                 FSP_ARRAY_LOAD(params->PchPseI2sSbInterruptEnable, config->PseI2sSbIntEn);
 172                 FSP_ARRAY_LOAD(params->PchPseSpiEnable, config->PseSpiOwn);
 173                 FSP_ARRAY_LOAD(params->PchPseSpiSbInterruptEnable, config->PseSpiSbIntEn);
 174                 FSP_ARRAY_LOAD(params->PchPseSpiCs0Enable, config->PseSpiCs0Own);
 175                 FSP_ARRAY_LOAD(params->PchPseSpiCs1Enable, config->PseSpiCs1Own);
 176                 FSP_ARRAY_LOAD(params->PchPseCanEnable, config->PseCanOwn);
 177                 FSP_ARRAY_LOAD(params->PchPseCanSbInterruptEnable, config->PseCanSbIntEn);
 178                 params->PchPsePwmEnable = config->PsePwmOwn;
 179                 params->PchPsePwmSbInterruptEnable = config->PsePwmSbIntEn;
 180                 FSP_ARRAY_LOAD(params->PchPsePwmPinEnable, config->PsePwmPinEn);
 181                 params->PchPseAdcEnable = config->PseAdcOwn;
 182                 params->PchPseAdcSbInterruptEnable = config->PseAdcSbIntEn;
 183                 params->PchPseLh2PseSbInterruptEnable = config->PseLh2PseSbIntEn;
 184                 params->PchPseShellEnabled = config->PseShellEn;
 185
 186                 /*
 187                  * As a minimum requirement for PSE initialization, the configuration
 188                  * of devices below are required as shown.
 189                  * TODO: Help needed to find a better way to handle this part of code
 190                  * as the settings from devicetree are overwritten here.
 191                  *
 192                  * Set the ownership of these devices to PSE. These are hardcoded for now,
 193                  * if the PSE should be opened one day (hopefully), this can be handled
 194                  * much better.
 195                  */
 196                 params->PchPseDmaEnable[0] = PSE_Owned;
 197                 params->PchPseUartEnable[2] = PSE_Owned;
 198                 params->PchPseHsuartEnable[2] = PSE_Owned;
 199                 params->PchPseI2cEnable[2] = PSE_Owned;
 200                 params->PchPseTimedGpioEnable[0] = PSE_Owned;
 201                 params->PchPseTimedGpioEnable[1] = PSE_Owned;
 202                 /* Disable PSE DMA Sideband Interrupt for DMA 0 */
 203                 params->PchPseDmaSbInterruptEnable[0] = 0;
 204                 /* Set the log output to PSE UART 2 */
 205                 params->PchPseLogOutputChannel = 3;
 206         } else {
 207                 die("PSE enabled but PSE FW not available!\n");
 208         }
 209 }
 210
 211 static void parse_devicetree(FSP_S_CONFIG *params)
 212 {
 213         const struct soc_intel_elkhartlake_config *config = config_of_soc();
 214
 215         /* LPSS controllers configuration */
 216
 217         /* I2C */
 218         FSP_ARRAY_LOAD(params->SerialIoI2cMode, config->SerialIoI2cMode);
 219         FSP_ARRAY_LOAD(params->PchSerialIoI2cPadsTermination,
 220                 config->SerialIoI2cPadsTermination);
 221
 222         params->PchSerialIoI2cSclPinMux[4] = 0x1B44AC09;        //GPIO native mode for GPP_H9
 223         params->PchSerialIoI2cSdaPinMux[4] = 0x1B44CC08;        //GPIO native mode for GPP_H8
 224
 225         /* GSPI */
 226         FSP_ARRAY_LOAD(params->SerialIoSpiMode, config->SerialIoGSpiMode);
 227         FSP_ARRAY_LOAD(params->SerialIoSpiCsEnable, config->SerialIoGSpiCsEnable);
 228         FSP_ARRAY_LOAD(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode);
 229         FSP_ARRAY_LOAD(params->SerialIoSpiCsState, config->SerialIoGSpiCsState);
 230         params->SerialIoSpiCsPolarity[2] = 0;
 231
 232         /* UART */
 233         FSP_ARRAY_LOAD(params->SerialIoUartMode, config->SerialIoUartMode);
 234         FSP_ARRAY_LOAD(params->SerialIoUartDmaEnable, config->SerialIoUartDmaEnable);
 235
 236         params->SerialIoUartCtsPinMuxPolicy[0] = 0x2B01320F;    //GPIO native mode for GPP_T15
 237         params->SerialIoUartRtsPinMuxPolicy[0] = 0x2B01220E;    //GPIO native mode for GPP_T14
 238         params->SerialIoUartRxPinMuxPolicy[0] = 0x2B01020C;     //GPIO native mode for GPP_T12
 239         params->SerialIoUartTxPinMuxPolicy[0] = 0x2B01120D;     //GPIO native mode for GPP_T13
 240
 241         /* Provide correct UART number for FSP debug logs */
 242         params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
 243 }
 244
 245 /* UPD parameters to be initialized before SiliconInit */
 246 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 247 {
 248         unsigned int i;
 249
 250         FSP_S_CONFIG *params = &supd->FspsConfig;
 251         struct soc_intel_elkhartlake_config *config = config_of_soc();
 252
 253         /* Parse device tree and fill in FSP UPDs */
 254         parse_devicetree(params);
 255
 256         /* Load VBT before devicetree-specific config. */
 257         params->GraphicsConfigPtr = (uintptr_t)vbt_get();
 258
 259         /* Check if IGD is present and fill Graphics init param accordingly */
 260         params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
 261
 262         /* Display config */
 263         params->DdiPortAConfig = config->DdiPortAConfig;
 264         params->DdiPortBConfig = config->DdiPortBConfig;
 265         params->DdiPortCConfig = config->DdiPortCConfig;
 266         params->DdiPortAHpd = config->DdiPortAHpd;
 267         params->DdiPortBHpd = config->DdiPortBHpd;
 268         params->DdiPortCHpd = config->DdiPortCHpd;
 269         params->DdiPort1Hpd = config->DdiPort1Hpd;
 270         params->DdiPort2Hpd = config->DdiPort2Hpd;
 271         params->DdiPort3Hpd = config->DdiPort3Hpd;
 272         params->DdiPort4Hpd = config->DdiPort4Hpd;
 273         params->DdiPortADdc = config->DdiPortADdc;
 274         params->DdiPortBDdc = config->DdiPortBDdc;
 275         params->DdiPortCDdc = config->DdiPortCDdc;
 276         params->DdiPort1Ddc = config->DdiPort1Ddc;
 277         params->DdiPort2Ddc = config->DdiPort2Ddc;
 278         params->DdiPort3Ddc = config->DdiPort3Ddc;
 279         params->DdiPort4Ddc = config->DdiPort4Ddc;
 280
 281         /* Intel Speed Step */
 282         params->Eist = config->eist_enable;
 283
 284         /* Use coreboot MP PPI services if Kconfig is enabled */
 285         if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
 286                 params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
 287
 288         /* Chipset Lockdown */
 289         if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
 290                 params->PchLockDownGlobalSmi = 0;
 291                 params->PchLockDownBiosLock = 0;
 292                 params->PchLockDownBiosInterface = 0;
 293                 params->PchWriteProtectionEnable[0] = 0;
 294                 params->PchUnlockGpioPads = 1;
 295                 params->RtcMemoryLock = 0;
 296                 params->SkipPamLock = 1;
 297         } else {
 298                 params->PchLockDownGlobalSmi = 1;
 299                 params->PchLockDownBiosLock = 1;
 300                 params->PchLockDownBiosInterface = 1;
 301                 params->PchWriteProtectionEnable[0] = 1;
 302                 params->PchUnlockGpioPads = 0;
 303                 params->RtcMemoryLock = 1;
 304                 params->SkipPamLock = 0;
 305         }
 306
 307         /* Disable PAVP */
 308         params->PavpEnable = 0;
 309
 310         /* Legacy 8254 timer support */
 311         bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
 312         params->Enable8254ClockGating = !use_8254;
 313         params->Enable8254ClockGatingOnS3 = 1;
 314
 315         /*
 316          * Legacy PM ACPI Timer (and TCO Timer)
 317          * This *must* be 1 in any case to keep FSP from
 318          *  1) enabling PM ACPI Timer emulation in uCode.
 319          *  2) disabling the PM ACPI Timer.
 320          * We handle both by ourself!
 321          */
 322         params->EnableTcoTimer = 1;
 323
 324         /* Set up recommended real time parameters if real time tuning is enabled. */
 325         if (config->realtime_tuning_enable) {
 326                 params->PchPostMasterClockGating = 0;
 327                 params->PchPostMasterPowerGating = 0;
 328                 params->PchPwrOptEnable = 0;
 329                 params->PsfTccEnable = 1;
 330                 params->PmcLpmS0ixSubStateEnableMask = 0;
 331                 params->PchDmiAspmCtrl = 0;
 332                 params->PchLegacyIoLowLatency = 0;
 333                 params->EnableItbm = 0;
 334                 params->D3ColdEnable = 0;
 335                 params->PmcOsIdleEnable = 0;
 336         } else {
 337                 params->PchPwrOptEnable = 1; /* Enable PCH DMI Power Optimizer */
 338                 params->PchPostMasterClockGating = 1;
 339                 params->PchPostMasterPowerGating = 1;
 340         }
 341         /* HECI */
 342         params->Heci3Enabled = config->Heci3Enable;
 343
 344         /* USB configuration */
 345         for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
 346                 params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
 347                 params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
 348                 params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
 349                 params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
 350                 params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
 351                 params->Usb2OverCurrentPin[i] = config->usb2_ports[i].enable ?
 352                         config->usb2_ports[i].ocpin : 0xff;
 353         }
 354
 355         for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
 356                 params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
 357                 params->Usb3OverCurrentPin[i] = config->usb3_ports[i].enable ?
 358                         config->usb3_ports[i].ocpin : 0xff;
 359                 if (config->usb3_ports[i].tx_de_emp) {
 360                         params->Usb3HsioTxDeEmphEnable[i] = 1;
 361                         params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
 362                 }
 363                 if (config->usb3_ports[i].tx_downscale_amp) {
 364                         params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
 365                         params->Usb3HsioTxDownscaleAmp[i] =
 366                                 config->usb3_ports[i].tx_downscale_amp;
 367                 }
 368         }
 369
 370         params->UsbClockGatingEnable = 1;
 371         params->UsbPowerGatingEnable = 1;
 372
 373         params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG);
 374
 375         /* PCIe root ports config */
 376         for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
 377                 params->PcieRpClkReqDetect[i] =
 378                         !config->PcieRpClkReqDetectDisable[i];
 379                 params->PcieRpL1Substates[i] =
 380                         get_l1_substate_control(config->PcieRpL1Substates[i]);
 381                 params->PcieRpLtrEnable[i] = !config->PcieRpLtrDisable[i];
 382                 params->PcieRpAdvancedErrorReporting[i] =
 383                         !config->PcieRpAdvancedErrorReportingDisable[i];
 384                 params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
 385                 params->PciePtm[i] = config->PciePtm[i];
 386                 params->PcieRpPcieSpeed[i] = config->PcieRpPcieSpeed[i];
 387                 params->PcieRpLtrMaxNoSnoopLatency[i] = 0x1003;
 388                 params->PcieRpLtrMaxSnoopLatency[i] = 0x1003;
 389                 /* Virtual Channel 1 to Traffic Class mapping */
 390                 params->PcieRpVc1TcMap[i] = 0x60;
 391                 if (config->realtime_tuning_enable)
 392                         params->PcieRpEnableCpm[i] = 0;
 393                 params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
 394         }
 395
 396         /* SATA config */
 397         params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
 398         if (params->SataEnable) {
 399                 params->SataMode = config->SataMode;
 400                 params->SataSalpSupport = config->SataSalpSupport;
 401                 params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
 402                 params->SataSpeedLimit = config->SataSpeed;
 403
 404                 for (i = 0; i < CONFIG_MAX_SATA_PORTS; i++) {
 405                         params->SataPortsEnable[i] = config->SataPortsEnable[i];
 406                         params->SataPortsDevSlp[i] = config->SataPortsDevSlp[i];
 407                         params->SataPortsSolidStateDrive[i] = config->SataPortsSSD[i];
 408                         if (config->SataPortsEnableDitoConfig[i]) {
 409                                 params->SataPortsDmVal[i] =
 410                                         config->SataPortsDmVal[i] ? : DEF_DMVAL;
 411                                 params->SataPortsDitoVal[i] =
 412                                         config->SataPortsDitoVal[i] ? : DEF_DITOVAL_MS;
 413                         }
 414                 }
 415         }
 416
 417         /* SDCard config */
 418         params->ScsSdCardEnabled = is_devfn_enabled(PCH_DEVFN_SDCARD);
 419         if (params->ScsSdCardEnabled) {
 420                 params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh;
 421                 params->SdCardGpioCmdPadTermination = GPIO_TERM_NATIVE;
 422                 params->SdCardGpioDataPadTermination[0] = GPIO_TERM_NATIVE;
 423                 params->SdCardGpioDataPadTermination[1] = GPIO_TERM_NATIVE;
 424                 params->SdCardGpioDataPadTermination[2] = GPIO_TERM_NATIVE;
 425                 params->SdCardGpioDataPadTermination[3] = GPIO_TERM_NATIVE;
 426         }
 427
 428         /* eMMC config */
 429         params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC);
 430         if (params->ScsEmmcEnabled) {
 431                 params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
 432                 params->ScsEmmcDdr50Enabled = config->ScsEmmcDdr50Enabled;
 433         }
 434
 435         /* Thermal config */
 436         params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF);
 437         params->ProcHotResponse = 0x0;  //Disable PROCHOT response
 438         /* Thermal sensor (TS) target width */
 439         params->DmiTS0TW = 3;
 440         params->DmiTS1TW = 2;
 441         params->DmiTS2TW = 1;
 442         /* Enable memory thermal throttling by default */
 443         if (!config->MemoryThermalThrottlingDisable) {
 444                 params->PchMemoryPmsyncEnable[0] = 1;
 445                 params->PchMemoryPmsyncEnable[1] = 1;
 446                 params->PchMemoryC0TransmitEnable[0] = 1;
 447                 params->PchMemoryC0TransmitEnable[1] = 1;
 448         }
 449
 450         /* TccActivationOffset config */
 451         params->TccActivationOffset = config->tcc_offset;
 452         params->TccOffsetClamp = config->tcc_offset_clamp;
 453         params->TccOffsetLock = 0x1;    //lock Tcc Offset register
 454
 455         /* Power management config */
 456         params->ImonSlope[0] = IMON_SLOPE;
 457         params->ImonOffset[0] = IMON_OFFSET;
 458         params->TdcCurrentLimit[0] = TDC_CURRENT_LIMIT_MAX;
 459         params->AcLoadline[0] = AC_LOADLINE_LANE_0_MAX;
 460         params->DcLoadline[0] = DC_LOADLINE_LANE_0_MAX;
 461         params->AcLoadline[1] = AC_LOADLINE_LANE_1_MAX;
 462         params->DcLoadline[1] = DC_LOADLINE_LANE_1_MAX;
 463         params->IccMax[0] = ICC_LIMIT_MAX;
 464         params->OneCoreRatioLimit = CORE_RATIO_LIMIT;
 465         params->TwoCoreRatioLimit = CORE_RATIO_LIMIT;
 466         params->ThreeCoreRatioLimit = CORE_RATIO_LIMIT;
 467         params->FourCoreRatioLimit = CORE_RATIO_LIMIT;
 468         params->FiveCoreRatioLimit = CORE_RATIO_LIMIT;
 469         params->SixCoreRatioLimit = CORE_RATIO_LIMIT;
 470         params->SevenCoreRatioLimit = CORE_RATIO_LIMIT;
 471         params->EightCoreRatioLimit = CORE_RATIO_LIMIT;
 472         params->PsysPmax = 0;   //Set max platform power to auto profile
 473         params->Custom1TurboActivationRatio = 0;
 474         params->Custom2TurboActivationRatio = 0;
 475         params->Custom3TurboActivationRatio = 0;
 476         params->TStates = 0x0;  //Disable T state
 477         params->PkgCStateLimit = 0x7;   //Set C state limit to C9
 478         params->FastPkgCRampDisable[0] = 0x1;
 479         params->SlowSlewRate[0] = 0x1;
 480         params->MaxRatio = 0x8; //Set max P state ratio
 481         params->PchEspiLgmrEnable = 0;
 482         params->PchPmPwrBtnOverridePeriod = config->PchPmPwrBtnOverridePeriod;
 483         params->PchS0ixAutoDemotion = 0;
 484         params->PmcV1p05PhyExtFetControlEn = 0x1;
 485         params->PmcV1p05IsExtFetControlEn = 0x1;
 486         /* FIVR config */
 487         if (config->fivr.fivr_config_en) {
 488                 fill_fsps_fivr_params(params, config);
 489         }
 490
 491         /* FuSa (Functional Safety) config */
 492         if (!config->FuSaEnable) {
 493                 params->DisplayFusaConfigEnable = 0;
 494                 params->GraphicFusaConfigEnable = 0;
 495                 params->OpioFusaConfigEnable = 0;
 496                 params->PsfFusaConfigEnable = 0;
 497         }
 498
 499         /* PSE (Intel Programmable Services Engine) config */
 500         if (CONFIG(PSE_ENABLE) && cbfs_file_exists("pse.bin"))
 501                 fill_fsps_pse_params(params, config);
 502
 503         /* TSN GBE config */
 504         fill_fsps_tsn_params(params, config);
 505
 506         /* Override/Fill FSP Silicon Param for mainboard */
 507         mainboard_silicon_init_params(params);
 508 }
 509
 510 /* Mainboard GPIO Configuration */
 511 __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 512 {
 513         printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 514 }