soc/mediatek/mt8196: Initialize SSPM
[coreboot.git] / src / soc / intel / jasperlake / acpi / southbridge.asl
blob63b2dfa152a498d8e553dd90a66c65aa1461c8b8
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <intelblocks/itss.h>
4 #include <intelblocks/pcr.h>
5 #include <soc/pcr_ids.h>
7 /* PCI IRQ assignment */
8 #include "pci_irqs.asl"
10 /* PCR access */
11 #include <soc/intel/common/acpi/pch_pcr.asl>
13 /* PCH clock */
14 #include "camera_clock_ctl.asl"
16 /* GPIO controller */
17 #include "gpio.asl"
19 /* ESPI 0:1f.0 */
20 #include <soc/intel/common/block/acpi/acpi/lpc.asl>
22 /* PCH HDA */
23 #include "pch_hda.asl"
25 /* PCIE Ports */
26 #include "pcie.asl"
28 /* pmc 0:1f.2 */
29 #include "pmc.asl"
31 /* Serial IO */
32 #include "serialio.asl"
34 /* SMBus 0:1f.4 */
35 #include <soc/intel/common/block/acpi/acpi/smbus.asl>
37 /* ISH 0:12.0 */
38 #include <soc/intel/common/block/acpi/acpi/ish.asl>
40 /* USB XHCI 0:14.0 */
41 #include "xhci.asl"
43 /* PCI _OSC */
44 #include <soc/intel/common/acpi/pci_osc.asl>
46 /* EMMC/SD card */
47 #include "scs.asl"
49 /* GbE 0:1f.6 */
50 #include <soc/intel/common/block/acpi/acpi/pch_glan.asl>