MAINTAINERS: Add Yuchi and Vasiliy for Intel Atom Snow Ridge SoC
[coreboot.git] / src / soc / intel / jasperlake / xhci.c
blob55ed9c789a1f5d11a9283e31430cc690a9749df0
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <console/console.h>
4 #include <device/mmio.h>
5 #include <intelblocks/xhci.h>
6 #include <soc/soc_chip.h>
7 #include <static.h>
9 #define XHCI_USB2_PORT_STATUS_REG 0x480
10 #define XHCI_USB3_PORT_STATUS_REG 0x500
11 #define XHCI_USB2_PORT_NUM 8
12 #define XHCI_USB3_PORT_NUM 6
14 #define XHCI_PMCTRL 0x80A4
15 /* BIT[7:4] LFPS periodic sampling off time for USB3 Ports */
16 #define PMCTRL_LFPS_OFFTIME_SHIFT 4
17 #define PMCTRL_LFPS_OFFTIME_MAX 0xF
19 static const struct xhci_usb_info usb_info = {
20 .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG,
21 .num_usb2_ports = XHCI_USB2_PORT_NUM,
22 .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG,
23 .num_usb3_ports = XHCI_USB3_PORT_NUM,
26 const struct xhci_usb_info *soc_get_xhci_usb_info(pci_devfn_t xhci_dev)
28 /* Jasper Lake only has one XHCI controller */
29 return &usb_info;
32 static void set_xhci_lfps_sampling_offtime(struct device *dev, uint8_t time_ms)
34 void *addr;
35 const struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0);
37 if (!res)
38 return;
40 if (time_ms > PMCTRL_LFPS_OFFTIME_MAX) {
41 printk(BIOS_ERR,
42 "XHCI: The maximum LFPS sampling OFF time is %u ms, "
43 "cannot set it to %u ms\n",
44 PMCTRL_LFPS_OFFTIME_MAX, time_ms);
46 return;
49 addr = (void *)(uintptr_t)(res->base + XHCI_PMCTRL);
50 clrsetbits32(addr,
51 PMCTRL_LFPS_OFFTIME_MAX << PMCTRL_LFPS_OFFTIME_SHIFT,
52 time_ms << PMCTRL_LFPS_OFFTIME_SHIFT);
53 printk(BIOS_DEBUG,
54 "XHCI: Updated LFPS sampling OFF time to %u ms\n", time_ms);
57 void soc_xhci_init(struct device *dev)
59 const config_t *config = config_of_soc();
61 /* Set xHCI LFPS period sampling off time */
62 set_xhci_lfps_sampling_offtime(dev,
63 config->xhci_lfps_sampling_offtime_ms);