src/soc/intel/meteorlake/pcie_rp.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <intelblocks/pcie_rp.h>
   4 #include <soc/pci_devs.h>
   5 #include <soc/pcie.h>
   6 #include <soc/soc_info.h>
   7
   8 /*
   9  * Document #640228 Meteor Lake - U/H and U Type4 Processor - 2.3 Device IDs - Table 8 "Other
  10  * Device ID" specifies that the first Thunderbolt PCIe root port number is 16. TBT's LCAP
  11  * registers return port index which starts from 16 (usually for other PCIe root ports index
  12  * starts from 1). Thus, keeping lcap_port_base 16 for TBT, so that coreboot's PCIe remapping
  13  * logic can return a correct index (0-based).
  14  */
  15
  16 static const struct pcie_rp_group tbt_rp_groups[] = {
  17         { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 16 },
  18         { 0 }
  19 };
  20
  21 static const struct pcie_rp_group mtlp_rp_groups[] = {
  22         { .slot = PCI_DEV_SLOT_PCIE_1, .start = 0, .count = 8, .lcap_port_base = 1 },
  23         { .slot = PCI_DEV_SLOT_PCIE_2, .start = 0, .count = 3, .lcap_port_base = 1 },
  24         { .slot = PCI_DEV_SLOT_PCIE_3, .start = 0, .count = 1, .lcap_port_base = 1 },
  25         { 0 }
  26 };
  27
  28 const struct pcie_rp_group *get_pcie_rp_table(void)
  29 {
  30         return mtlp_rp_groups;
  31 }
  32
  33 const struct pcie_rp_group *get_tbt_pcie_rp_table(void)
  34 {
  35         return tbt_rp_groups;
  36 }
  37
  38 enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev)
  39 {
  40         return PCIE_RP_PCH;
  41 }
  42
  43 int soc_get_cpu_rp_vw_idx(const struct device *dev)
  44 {
  45         return -1;
  46 }