src/soc/intel/meteorlake/systemagent.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/ioapic.h>
   4 #include <console/console.h>
   5 #include <cpu/x86/msr.h>
   6 #include <device/device.h>
   7 #include <device/pci.h>
   8 #include <intelblocks/cpulib.h>
   9 #include <intelblocks/msr.h>
  10 #include <intelblocks/power_limit.h>
  11 #include <intelblocks/systemagent.h>
  12 #include <soc/iomap.h>
  13 #include <soc/soc_chip.h>
  14 #include <soc/systemagent.h>
  15 #include <static.h>
  16
  17 /*
  18  * SoC implementation
  19  *
  20  * Add all known fixed memory ranges for Host Controller/Memory
  21  * controller.
  22  */
  23 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
  24 {
  25         static const struct sa_mmio_descriptor soc_fixed_resources[] = {
  26                 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
  27                 { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
  28                 { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
  29                 { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
  30                 { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
  31
  32                 /* first field (sa_mmio_descriptor.index) is not used, setting to 0: */
  33                 { 0, CRAB_ABORT_BASE_ADDR, CRAB_ABORT_SIZE, "CRAB_ABORT" },
  34                 { 0, LT_SECURITY_BASE_ADDR, LT_SECURITY_SIZE, "LT_SECURITY" },
  35                 { 0, IO_APIC_ADDR, APIC_SIZE, "APIC" },
  36                 // PCH_PRESERVERD covers:
  37                 // TraceHub SW BAR, PMC MBAR, SPI BAR0, SerialIo BAR in ACPI mode
  38                 // eSPI LGMR BAR, eSPI2 SEGMR BAR, TraceHub MTB BAR, TraceHub FW BAR
  39                 // IOE PMC BAR, Tracehub RTIT BAR (SOC), HECI{1,2,3} BAR0
  40                 // see fsp/ClientOneSiliconPkg/Fru/MtlSoc/Include/PchReservedResources.h
  41                 { 0, PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE, "PCH_RESERVED" },
  42         };
  43
  44         sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
  45                         ARRAY_SIZE(soc_fixed_resources));
  46
  47         /* Add Vt-d resources if VT-d is enabled */
  48         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
  49                 return;
  50
  51         sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
  52                         ARRAY_SIZE(soc_vtd_resources));
  53 }
  54
  55 /*
  56  * set MMIO resource's fields
  57  */
  58 static void set_mmio_resource(
  59         struct sa_mmio_descriptor *resource,
  60         uint64_t base,
  61         uint64_t size,
  62         const char *description)
  63 {
  64         if (resource == NULL) {
  65                 printk(BIOS_ERR, "%s: argument resource is NULL for %s\n",
  66                 __func__, description);
  67                 return;
  68         }
  69         resource->base = base;
  70         resource->size = size;
  71         resource->description = description;
  72 }
  73
  74 int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base,
  75         uint64_t *prmrr_mask)
  76 {
  77         msr_t msr;
  78         msr = rdmsr(MSR_PRMRR_BASE_0);
  79         *prmrr_base = (uint64_t)msr.hi << 32 | msr.lo;
  80         msr = rdmsr(MSR_PRMRR_PHYS_MASK);
  81         *prmrr_mask = (uint64_t)msr.hi << 32 | msr.lo;
  82         return 0;
  83 }
  84
  85 /*
  86  * SoC implementation
  87  *
  88  * Add all known configurable memory ranges for Host Controller/Memory
  89  * controller.
  90  */
  91 void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt)
  92 {
  93         uint64_t size, base, tseg_base;
  94         int count = 0;
  95         struct sa_mmio_descriptor cfg_rsrc[6]; /* Increase size when adding more resources */
  96
  97         /* MMCONF */
  98         size = sa_get_mmcfg_size();
  99         if (size > 0)
 100                 set_mmio_resource(&(cfg_rsrc[count++]), CONFIG_ECAM_MMCONF_BASE_ADDRESS,
 101                         size, "MMCONF");
 102
 103         /* DSM */
 104         size = sa_get_dsm_size();
 105         if (size > 0) {
 106                 base = pci_read_config32(dev, BDSM) & 0xFFF00000;
 107                 set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DSM");
 108         }
 109
 110         /* TSEG */
 111         size = sa_get_tseg_size();
 112         tseg_base = sa_get_tseg_base();
 113         if (size > 0)
 114                 set_mmio_resource(&(cfg_rsrc[count++]), tseg_base, size, "TSEG");
 115
 116         /* PMRR */
 117         size = get_valid_prmrr_size();
 118         if (size > 0) {
 119                 uint64_t mask;
 120                 if (soc_get_uncore_prmmr_base_and_mask(&base, &mask) == 0) {
 121                         base &= mask;
 122                         set_mmio_resource(&(cfg_rsrc[count++]), base, size, "PMRR");
 123                 } else {
 124                         printk(BIOS_ERR, "SA: Failed to get PRMRR base and mask\n");
 125                 }
 126         }
 127
 128         /* GSM */
 129         size = sa_get_gsm_size();
 130         if (size > 0) {
 131                 base = sa_get_gsm_base();
 132                 set_mmio_resource(&(cfg_rsrc[count++]), base, size, "GSM");
 133         }
 134
 135         /* DPR */
 136         size = sa_get_dpr_size();
 137         if (size > 0) {
 138                 /* DPR just below TSEG: */
 139                 base = tseg_base - size;
 140                 set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DPR");
 141         }
 142
 143         /* Add all the above */
 144         sa_add_fixed_mmio_resources(dev, resource_cnt, cfg_rsrc, count);
 145 }
 146
 147 static void configure_tdp(struct device *dev)
 148 {
 149         struct soc_power_limits_config *soc_config;
 150         struct device *sa;
 151         uint16_t sa_pci_id;
 152         u8 tdp;
 153         size_t i;
 154         bool config_tdp = false;
 155         config_t *config;
 156
 157         config = config_of_soc();
 158
 159         /* Get System Agent PCI ID */
 160         sa = pcidev_path_on_root(PCI_DEVFN_ROOT);
 161         sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
 162
 163         if (sa_pci_id == 0xFFFF) {
 164                 printk(BIOS_WARNING, "Unknown SA PCI Device!\n");
 165                 return;
 166         }
 167
 168         tdp = get_cpu_tdp();
 169
 170         /*
 171          * Choose power limits configuration based on the CPU SA PCI ID and
 172          * CPU TDP value.
 173          */
 174         for (i = 0; i < ARRAY_SIZE(cpuid_to_mtl); i++) {
 175                 if (sa_pci_id == cpuid_to_mtl[i].cpu_id &&
 176                                 tdp == cpuid_to_mtl[i].cpu_tdp) {
 177                         soc_config = &config->power_limits_config[cpuid_to_mtl[i].limits];
 178                         set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
 179                         config_tdp = true;
 180                         printk(BIOS_DEBUG, "Configured power limits for SA PCI ID: 0x%4x\n",
 181                                 sa_pci_id);
 182                         break;
 183                 }
 184         }
 185
 186         if (!config_tdp) {
 187                 printk(BIOS_WARNING, "Skipped power limits configuration for SA PCI ID: 0x%4x\n",
 188                         sa_pci_id);
 189                 return;
 190         }
 191 }
 192
 193 /*
 194  * SoC implementation
 195  *
 196  * Perform System Agent Initialization during ramstage phase.
 197  */
 198 void soc_systemagent_init(struct device *dev)
 199 {
 200         /* Enable Power Aware Interrupt Routing */
 201         enable_power_aware_intr();
 202
 203         /* Configure TDP */
 204         configure_tdp(dev);
 205 }
 206
 207 uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
 208 {
 209         switch (capid0_a_ddrsz) {
 210         case 1:
 211                 return 8192;
 212         case 2:
 213                 return 4096;
 214         case 3:
 215                 return 2048;
 216         default:
 217                 return 65536;
 218         }
 219 }