src/soc/intel/pantherlake/acpi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <acpi/acpi_gnvs.h>
   5 #include <acpi/acpigen.h>
   6 #include <arch/ioapic.h>
   7 #include <arch/smp/mpspec.h>
   8 #include <console/console.h>
   9 #include <device/device.h>
  10 #include <device/mmio.h>
  11 #include <device/pci_ops.h>
  12 #include <fw_config.h>
  13 #include <intelblocks/cpulib.h>
  14 #include <intelblocks/pmclib.h>
  15 #include <intelblocks/acpi.h>
  16 #include <soc/cpu.h>
  17 #include <soc/iomap.h>
  18 #include <soc/nvs.h>
  19 #include <soc/pci_devs.h>
  20 #include <soc/pm.h>
  21 #include <soc/soc_chip.h>
  22 #include <soc/systemagent.h>
  23 #include <static.h>
  24 #include <types.h>
  25
  26 /*
  27  * TODO: Update as per PTL spec.
  28  * List of supported C-states in this processor.
  29  */
  30 enum {
  31         C_STATE_C0,             /* 0 */
  32         C_STATE_C1,             /* 1 */
  33         C_STATE_C1E,            /* 2 */
  34         C_STATE_C6_SHORT_LAT,   /* 3 */
  35         C_STATE_C6_LONG_LAT,    /* 4 */
  36         C_STATE_C7_SHORT_LAT,   /* 5 */
  37         C_STATE_C7_LONG_LAT,    /* 6 */
  38         C_STATE_C7S_SHORT_LAT,  /* 7 */
  39         C_STATE_C7S_LONG_LAT,   /* 8 */
  40         C_STATE_C8,             /* 9 */
  41         C_STATE_C9,             /* 10 */
  42         C_STATE_C10,            /* 11 */
  43         NUM_C_STATES
  44 };
  45
  46 /* TODO: Update as per PTL spec. */
  47 static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
  48         [C_STATE_C0] = {},
  49         [C_STATE_C1] = {
  50                 .latency = C1_LATENCY,
  51                 .power = C1_POWER,
  52                 .resource = MWAIT_RES(0, 0),
  53         },
  54         [C_STATE_C1E] = {
  55                 .latency = C1_LATENCY,
  56                 .power = C1_POWER,
  57                 .resource = MWAIT_RES(0, 1),
  58         },
  59         [C_STATE_C6_SHORT_LAT] = {
  60                 .latency = C6_LATENCY,
  61                 .power = C6_POWER,
  62                 .resource = MWAIT_RES(2, 0),
  63         },
  64         [C_STATE_C6_LONG_LAT] = {
  65                 .latency = C6_LATENCY,
  66                 .power = C6_POWER,
  67                 .resource = MWAIT_RES(2, 1),
  68         },
  69         [C_STATE_C7_SHORT_LAT] = {
  70                 .latency = C7_LATENCY,
  71                 .power = C7_POWER,
  72                 .resource = MWAIT_RES(3, 0),
  73         },
  74         [C_STATE_C7_LONG_LAT] = {
  75                 .latency = C7_LATENCY,
  76                 .power = C7_POWER,
  77                 .resource = MWAIT_RES(3, 1),
  78         },
  79         [C_STATE_C7S_SHORT_LAT] = {
  80                 .latency = C7_LATENCY,
  81                 .power = C7_POWER,
  82                 .resource = MWAIT_RES(3, 2),
  83         },
  84         [C_STATE_C7S_LONG_LAT] = {
  85                 .latency = C7_LATENCY,
  86                 .power = C7_POWER,
  87                 .resource = MWAIT_RES(3, 3),
  88         },
  89         [C_STATE_C8] = {
  90                 .latency = C8_LATENCY,
  91                 .power = C8_POWER,
  92                 .resource = MWAIT_RES(4, 0),
  93         },
  94         [C_STATE_C9] = {
  95                 .latency = C9_LATENCY,
  96                 .power = C9_POWER,
  97                 .resource = MWAIT_RES(5, 0),
  98         },
  99         [C_STATE_C10] = {
 100                 .latency = C10_LATENCY,
 101                 .power = C10_POWER,
 102                 .resource = MWAIT_RES(6, 0),
 103         },
 104 };
 105
 106 /* TODO: Update as per PTL spec */
 107 static int cstate_set_non_s0ix[] = {
 108         C_STATE_C1,
 109         C_STATE_C6_LONG_LAT,
 110         C_STATE_C7S_LONG_LAT
 111 };
 112
 113 /* TODO: Update as per PTL spec */
 114 static int cstate_set_s0ix[] = {
 115         C_STATE_C1,
 116         C_STATE_C6_LONG_LAT,
 117         C_STATE_C10
 118 };
 119
 120 const acpi_cstate_t *soc_get_cstate_map(size_t *entries)
 121 {
 122         static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix),
 123                                 ARRAY_SIZE(cstate_set_non_s0ix))];
 124         static bool c_state_initialized = false;
 125         size_t i;
 126
 127         if (c_state_initialized)
 128                 return map;
 129
 130         const struct soc_intel_pantherlake_config *config = config_of_soc();
 131         if (config == NULL) {
 132                 printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n");
 133                 return NULL;
 134         }
 135
 136         int *set;
 137         if (config->s0ix_enable) {
 138                 *entries = ARRAY_SIZE(cstate_set_s0ix);
 139                 set = cstate_set_s0ix;
 140         } else {
 141                 *entries = ARRAY_SIZE(cstate_set_non_s0ix);
 142                 set = cstate_set_non_s0ix;
 143         }
 144
 145         for (i = 0; i < *entries; i++) {
 146                 map[i] = cstate_map[set[i]];
 147                 map[i].ctype = i + 1;
 148         }
 149         c_state_initialized = true;
 150
 151         return map;
 152 }
 153
 154 void soc_power_states_generation(int core_id, int cores_per_package)
 155 {
 156         const struct soc_intel_pantherlake_config *config = config_of_soc();
 157         if (config == NULL) {
 158                 printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n");
 159                 return;
 160         }
 161         if (config->eist_enable)
 162                 /* Generate P-state tables */
 163                 generate_p_state_entries(core_id, cores_per_package);
 164 }
 165
 166 void soc_fill_fadt(acpi_fadt_t *fadt)
 167 {
 168         const uint16_t pmbase = ACPI_BASE_ADDRESS;
 169
 170         const struct soc_intel_pantherlake_config *config = config_of_soc();
 171         if (config == NULL) {
 172                 printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n");
 173                 return;
 174         }
 175         fadt->pm_tmr_blk = pmbase + PM1_TMR;
 176         fadt->pm_tmr_len = sizeof(uint32_t);
 177
 178         fill_fadt_extended_pm_io(fadt);
 179
 180         if (config->s0ix_enable)
 181                 fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 182 }
 183
 184 static struct min_sleep_state min_pci_sleep_states[] = {
 185         { SA_DEVFN_ROOT,        ACPI_DEVICE_SLEEP_D3 },
 186         { SA_DEVFN_IGD,         ACPI_DEVICE_SLEEP_D3 },
 187         { PCI_DEVFN_IPU,        ACPI_DEVICE_SLEEP_D3 },
 188         { PCI_DEVFN_TBT0,       ACPI_DEVICE_SLEEP_D3 },
 189         { PCI_DEVFN_TBT1,       ACPI_DEVICE_SLEEP_D3 },
 190         { PCI_DEVFN_TBT2,       ACPI_DEVICE_SLEEP_D3 },
 191         { PCI_DEVFN_TBT3,       ACPI_DEVICE_SLEEP_D3 },
 192         { PCI_DEVFN_TCSS_XHCI,  ACPI_DEVICE_SLEEP_D3 },
 193         { PCI_DEVFN_TCSS_XDCI,  ACPI_DEVICE_SLEEP_D3 },
 194         { SA_DEVFN_TCSS_DMA0,   ACPI_DEVICE_SLEEP_D3 },
 195         { SA_DEVFN_TCSS_DMA1,   ACPI_DEVICE_SLEEP_D3 },
 196         { PCI_DEVFN_THC0,       ACPI_DEVICE_SLEEP_D3 },
 197         { PCI_DEVFN_THC1,       ACPI_DEVICE_SLEEP_D3 },
 198         { PCH_DEVFN_XHCI,       ACPI_DEVICE_SLEEP_D3 },
 199         { PCI_DEVFN_USBOTG,     ACPI_DEVICE_SLEEP_D3 },
 200         { PCI_DEVFN_SRAM,       ACPI_DEVICE_SLEEP_D3 },
 201         { PCI_DEVFN_CNVI_WIFI,  ACPI_DEVICE_SLEEP_D3 },
 202         { PCI_DEVFN_I2C0,       ACPI_DEVICE_SLEEP_D3 },
 203         { PCI_DEVFN_I2C1,       ACPI_DEVICE_SLEEP_D3 },
 204         { PCI_DEVFN_I2C2,       ACPI_DEVICE_SLEEP_D3 },
 205         { PCI_DEVFN_I2C3,       ACPI_DEVICE_SLEEP_D3 },
 206         { PCH_DEVFN_CSE,        ACPI_DEVICE_SLEEP_D0 },
 207         { PCI_DEVFN_I2C4,       ACPI_DEVICE_SLEEP_D3 },
 208         { PCI_DEVFN_I2C5,       ACPI_DEVICE_SLEEP_D3 },
 209         { PCI_DEVFN_UART2,      ACPI_DEVICE_SLEEP_D3 },
 210         { PCI_DEVFN_PCIE1,      ACPI_DEVICE_SLEEP_D0 },
 211         { PCI_DEVFN_PCIE2,      ACPI_DEVICE_SLEEP_D0 },
 212         { PCI_DEVFN_PCIE3,      ACPI_DEVICE_SLEEP_D0 },
 213         { PCI_DEVFN_PCIE4,      ACPI_DEVICE_SLEEP_D0 },
 214         { PCI_DEVFN_PCIE5,      ACPI_DEVICE_SLEEP_D0 },
 215         { PCI_DEVFN_PCIE6,      ACPI_DEVICE_SLEEP_D0 },
 216         { PCI_DEVFN_PCIE7,      ACPI_DEVICE_SLEEP_D0 },
 217         { PCI_DEVFN_PCIE8,      ACPI_DEVICE_SLEEP_D0 },
 218         { PCI_DEVFN_PCIE9,      ACPI_DEVICE_SLEEP_D0 },
 219         { PCI_DEVFN_PCIE10,     ACPI_DEVICE_SLEEP_D0 },
 220         { PCI_DEVFN_PCIE11,     ACPI_DEVICE_SLEEP_D0 },
 221         { PCI_DEVFN_PCIE12,     ACPI_DEVICE_SLEEP_D0 },
 222         { PCI_DEVFN_UART0,      ACPI_DEVICE_SLEEP_D3 },
 223         { PCI_DEVFN_UART1,      ACPI_DEVICE_SLEEP_D3 },
 224         { PCI_DEVFN_GSPI0,      ACPI_DEVICE_SLEEP_D3 },
 225         { PCI_DEVFN_GSPI1,      ACPI_DEVICE_SLEEP_D3 },
 226         { PCI_DEVFN_ESPI,       ACPI_DEVICE_SLEEP_D0 },
 227         { PCH_DEVFN_PMC,        ACPI_DEVICE_SLEEP_D0 },
 228         { PCI_DEVFN_HDA,        ACPI_DEVICE_SLEEP_D0 },
 229         { PCI_DEVFN_SMBUS,      ACPI_DEVICE_SLEEP_D0 },
 230         { PCI_DEVFN_SPI,        ACPI_DEVICE_SLEEP_D3 },
 231         { PCI_DEVFN_GBE,        ACPI_DEVICE_SLEEP_D3 },
 232 };
 233
 234 struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size)
 235 {
 236         *size = ARRAY_SIZE(min_pci_sleep_states);
 237         return min_pci_sleep_states;
 238 }
 239
 240 uint32_t soc_read_sci_irq_select(void)
 241 {
 242         return read32p(soc_read_pmc_base() + IRQ_REG);
 243 }
 244
 245 static unsigned long soc_fill_dmar(unsigned long current)
 246 {
 247         uint32_t vtd_engine_enabled = MCHBAR32(GFXVTBAR);
 248         const uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
 249         bool is_ipu_enabled = is_devfn_enabled(PCI_DEVFN_IPU);
 250         bool is_dptf_enabled = is_devfn_enabled(PCI_DEVFN_DPTF);
 251         bool is_npu_enabled = is_devfn_enabled(PCI_DEVFN_NPU);
 252         bool is_iaa_enabled = is_devfn_enabled(PCI_DEVFN_IAA);
 253
 254         printk(BIOS_DEBUG, "%s - gfxvtbar:0x%llx  0x%x\n", __func__, gfxvtbar, MCHBAR32(GFXVTBAR));
 255         if (vtd_engine_enabled & GFXVT_ENABLED) {
 256                 const unsigned long tmp = current;
 257                 current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar, GFXVT_BASE_SIZE);
 258                 current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0);
 259
 260                 acpi_dmar_drhd_fixup(tmp, current);
 261         }
 262
 263         if ((is_ipu_enabled || is_dptf_enabled || is_npu_enabled || is_iaa_enabled) &&
 264                 (vtd_engine_enabled & NONGFXVT_ENABLED)) {
 265                 const unsigned long tmp = current;
 266                 current += acpi_create_dmar_drhd(current,
 267                         0, 0, (uint64_t)VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE);
 268                 if (is_ipu_enabled)
 269                         current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IPU, 0);
 270                 if (is_dptf_enabled)
 271                         current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_DPTF, 0);
 272                 if (is_npu_enabled)
 273                         current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_NPU, 0);
 274                 if (is_iaa_enabled)
 275                         current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IAA, 0);
 276
 277                 acpi_dmar_drhd_fixup(tmp, current);
 278         }
 279
 280         if (vtd_engine_enabled & IOCVT_ENABLED) {
 281                 const unsigned long tmp = current;
 282                 current += acpi_create_dmar_drhd(current,
 283                         DRHD_INCLUDE_PCI_ALL, 0, (uint64_t)IOCVTD_BASE_ADDRESS, IOCVTD_BASE_SIZE);
 284                 current += acpi_create_dmar_ds_ioapic_from_hw(current,
 285                         IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, V_P2SB_CFG_IBDF_FUNC);
 286                 current += acpi_create_dmar_ds_msi_hpet(current, 0, V_P2SB_CFG_HBDF_BUS,
 287                         V_P2SB_CFG_HBDF_DEV, V_P2SB_CFG_HBDF_FUNC);
 288
 289                 acpi_dmar_drhd_fixup(tmp, current);
 290         }
 291
 292         /* Add RMRR entry */
 293         if (vtd_engine_enabled & GFXVT_ENABLED) {
 294                 const unsigned long tmp = current;
 295                 current += acpi_create_dmar_rmrr(current, 0,
 296                                 sa_get_gsm_base(), sa_get_tolud_base() - 1);
 297                 current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0);
 298
 299                 acpi_dmar_rmrr_fixup(tmp, current);
 300         }
 301
 302         if (is_ipu_enabled || is_dptf_enabled || is_npu_enabled || is_iaa_enabled) {
 303                 const unsigned long tmp = current;
 304                 current += acpi_create_dmar_satc(current, ATC_REQUIRED, 0);
 305                         current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0);
 306                 if (is_dptf_enabled)
 307                         current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_DPTF, 0);
 308                 if (is_ipu_enabled)
 309                         current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IPU, 0);
 310                 if (is_npu_enabled)
 311                         current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_NPU, 0);
 312                 if (is_iaa_enabled)
 313                         current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IAA, 0);
 314
 315                 acpi_dmar_satc_fixup(tmp, current);
 316         }
 317         return current;
 318 }
 319
 320 unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current,
 321                                    struct acpi_rsdp *rsdp)
 322 {
 323         acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
 324
 325         /*
 326          * Create DMAR table only if we have VT-d capability and FSP does not override its
 327          * feature.
 328          */
 329         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) ||
 330             !(MCHBAR32(GFXVTBAR) & (GFXVT_ENABLED | NONGFXVT_ENABLED | IOCVT_ENABLED)))
 331                 return current;
 332
 333         printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
 334         acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar);
 335         current += dmar->header.length;
 336         current = acpi_align_current(current);
 337         acpi_add_table(rsdp, dmar);
 338
 339         return current;
 340 }
 341
 342 void soc_fill_gnvs(struct global_nvs *gnvs)
 343 {
 344         const struct soc_intel_pantherlake_config *config = config_of_soc();
 345         if (config == NULL) {
 346                 printk(BIOS_ERR, "Configuration could not be retrieved.\n");
 347                 return;
 348         }
 349         /* Enable DPTF based on mainboard configuration */
 350         gnvs->dpte = config->dptf_enable;
 351
 352         /* Set USB2/USB3 wake enable bitmaps. */
 353         gnvs->u2we = config->usb2_wake_enable_bitmap;
 354         gnvs->u3we = config->usb3_wake_enable_bitmap;
 355 }
 356
 357 int soc_madt_sci_irq_polarity(int sci)
 358 {
 359         return MP_IRQ_POLARITY_HIGH;
 360 }