src/soc/intel/snowridge/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef _SOC_SNOWRIDGE_CHIP_H_
   4 #define _SOC_SNOWRIDGE_CHIP_H_
   5
   6 #include <fsp/soc_binding.h>
   7 #include <intelblocks/cfg.h>
   8 #include <stdint.h>
   9
  10 /**
  11  * @brief Total number of domains. SNR needs two additional domains to handle
  12  * additional root bus in stack 2 (Intel Dynamic Load Balancer) and 7 (UBox1).
  13  */
  14 #define MAX_DOMAIN (BL_MAX_SOCKET * BL_MAX_LOGIC_IIO_STACK + 2)
  15
  16 struct snr_domain {
  17         uint8_t enabled;
  18         uint8_t personality;
  19         uint8_t bus_base;
  20         uint8_t bus_limit;
  21         uint16_t io_base;
  22         uint16_t io_limit;
  23         uint32_t mem32_base;
  24         uint32_t mem32_limit;
  25         uint64_t mem64_base;
  26         uint64_t mem64_limit;
  27         struct device *dev;
  28 };
  29
  30 struct soc_intel_snowridge_config {
  31         struct soc_intel_common_config common_soc_config;
  32
  33         uint32_t tcc_offset; /**< Needed by `common/block/cpulib.c`. */
  34         uint8_t eist_enable;
  35
  36         struct snr_domain domain[MAX_DOMAIN];
  37 };
  38
  39 typedef struct soc_intel_snowridge_config config_t;
  40
  41 #endif // _SOC_SNOWRIDGE_CHIP_H_