src/soc/intel/snowridge/systemagent.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/hpet.h>
   4 #include <arch/ioapic.h>
   5 #include <commonlib/bsd/helpers.h>
   6 #include <cpu/x86/lapic_def.h>
   7 #include <device/pci_ops.h>
   8 #include <intelblocks/systemagent_server.h>
   9 #include <soc/iomap.h>
  10 #include <soc/systemagent.h>
  11 #include <security/intel/txt/txt_register.h>
  12
  13 static bool get_vtd_bar(struct device *dev, uint64_t *base, uint64_t *size)
  14 {
  15         struct sa_server_mem_map_descriptor vtd_bar_descriptor = {
  16                 .reg_offset = VTBAR,
  17                 .is_64_bit = true,
  18                 .alignment = 4 * KiB, /* Bit(0) is VT-d enable bit. */
  19         };
  20
  21         if (!(pci_read_config32(dev, VTBAR) & VTD_CHIPSET_BASE_ADDRESS_ENABLE))
  22                 return false;
  23
  24         *base = sa_server_read_map_entry(PCI_BDF(dev), &vtd_bar_descriptor);
  25         *size = 4 * KiB;
  26         return true;
  27 }
  28
  29 static bool get_pcie_mmcfg_bar(struct device *dev, uint64_t *base, uint64_t *size)
  30 {
  31         /* The PCIe MMCFG limit in registers is not correct thus using the configuration value here. */
  32         *base = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
  33         *size = CONFIG_ECAM_MMCONF_LENGTH;
  34         return true;
  35 }
  36
  37 static bool get_dpr(struct device *dev, uint64_t *base, uint64_t *size)
  38 {
  39         union dpr_register dpr = { .raw = pci_read_config32(dev, DPR) };
  40         *size = dpr.size * MiB;
  41         /* DPR base is read as 0s so it is calculated based on the assumption that DPR is below TSEG. */
  42         *base = sa_server_get_tseg_base() - *size;
  43         return true;
  44 }
  45
  46 static bool get_tseg(struct device *dev, uint64_t *base, uint64_t *size)
  47 {
  48         *base = sa_server_get_tseg_base();
  49         *size = sa_server_get_tseg_size();
  50         return true;
  51 }
  52
  53 void sa_server_soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt)
  54 {
  55         struct sa_server_mmio_descriptor vtd_descriptor = {
  56                 .get_resource = get_vtd_bar,
  57                 .description = "VT-d BAR",
  58         };
  59
  60         sa_server_add_mmio_resources(dev, resource_cnt, &vtd_descriptor, 1);
  61
  62         if (!sa_server_is_on_pch_domain(dev))
  63                 return;
  64
  65         struct sa_server_mmio_descriptor mmio_descriptors[] = {
  66                 {
  67                         .get_resource = get_pcie_mmcfg_bar,
  68                         .description = "PCIe MMCFG BAR",
  69                 },
  70                 {
  71                         .get_resource = get_dpr,
  72                         .description = "DMA Protection Range",
  73                 },
  74                 {
  75                         .get_resource = get_tseg,
  76                         .description = "TSEG",
  77                 },
  78                 {
  79                         .base = RESERVED_BASE_ADDRESS,
  80                         .size = RESERVED_BASE_SIZE,
  81                         .description = "PCH Reserved",
  82                 },
  83                 {
  84                         .base = IO_APIC_ADDR,
  85                         .size = 1 * MiB,
  86                         .description = "I/O APIC",
  87                 },
  88                 {
  89                         .base = HPET_BASE_ADDRESS,
  90                         .size = 1 * MiB,
  91                         .description = "HPET/TXT/TPM",
  92                 },
  93                 {
  94                         .base = LAPIC_DEFAULT_BASE,
  95                         .size = 2 * MiB,
  96                         .description = "Local APIC",
  97                 },
  98         };
  99
 100         sa_server_add_mmio_resources(dev, resource_cnt, mmio_descriptors,
 101                                                 ARRAY_SIZE(mmio_descriptors));
 102 }