src/soc/intel/tigerlake/Kconfig

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 config SOC_INTEL_TIGERLAKE
   4         bool
   5         select ACPI_INTEL_HARDWARE_SLEEP_VALUES
   6         select ARCH_X86
   7         select BOOT_DEVICE_SUPPORTS_WRITES
   8         select CACHE_MRC_SETTINGS
   9         select CPU_INTEL_COMMON
  10         select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
  11         select CPU_SUPPORTS_INTEL_TME
  12         select CPU_SUPPORTS_PM_TIMER_EMULATION
  13         select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS
  14         select DISPLAY_FSP_VERSION_INFO if !FSP_TYPE_IOT
  15         select DRIVERS_USB_ACPI
  16         select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
  17         select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
  18         select FSP_COMPRESS_FSP_S_LZ4
  19         select FSP_M_XIP
  20         select GENERIC_GPIO_LIB
  21         select HAVE_FSP_GOP
  22         select HAVE_HYPERTHREADING
  23         select HAVE_INTEL_FSP_REPO
  24         select INTEL_DESCRIPTOR_MODE_CAPABLE
  25         select HAVE_SMI_HANDLER
  26         select IDT_IN_EVERY_STAGE
  27         select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM
  28         select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED
  29         select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
  30         select SF_MASK_2WAYS_PER_BIT if INTEL_CAR_NEM_ENHANCED
  31         select INTEL_GMA_ACPI
  32         select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
  33         select INTEL_GMA_VERSION_2
  34         select MP_SERVICES_PPI_V1
  35         select MRC_SETTINGS_PROTECT
  36         select PARALLEL_MP_AP_WORK
  37         select PLATFORM_USES_FSP2_2
  38         select PMC_GLOBAL_RESET_ENABLE_LOCK
  39         select SOC_INTEL_COMMON
  40         select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
  41         select SOC_INTEL_COMMON_BLOCK
  42         select SOC_INTEL_COMMON_BLOCK_ACPI
  43         select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
  44         select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
  45         select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
  46         select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
  47         select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ
  48         select SOC_INTEL_COMMON_BLOCK_CAR
  49         select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
  50         select SOC_INTEL_COMMON_BLOCK_CNVI
  51         select SOC_INTEL_COMMON_BLOCK_CPU
  52         select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
  53         select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
  54         select SOC_INTEL_COMMON_BLOCK_DTT
  55         select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
  56         select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY
  57         select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
  58         select SOC_INTEL_COMMON_BLOCK_HDA
  59         select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
  60         select SOC_INTEL_COMMON_BLOCK_IRQ
  61         select SOC_INTEL_COMMON_BLOCK_ME_SPEC_15
  62         select SOC_INTEL_COMMON_BLOCK_MEMINIT
  63         select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
  64         select SOC_INTEL_COMMON_BLOCK_PMC_EPOC
  65         select SOC_INTEL_COMMON_BLOCK_SA
  66         select SOC_INTEL_COMMON_BLOCK_SMM
  67         select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
  68         select SOC_INTEL_COMMON_BLOCK_TCSS
  69         select SOC_INTEL_COMMON_BLOCK_USB4
  70         select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
  71         select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
  72         select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
  73         select SOC_INTEL_COMMON_FSP_RESET
  74         select SOC_INTEL_COMMON_PCH_CLIENT
  75         select SOC_INTEL_COMMON_RESET
  76         select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
  77         select SOC_INTEL_CSE_SEND_EOP_LATE
  78         select SOC_INTEL_CSE_SET_EOP
  79         select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
  80         select SSE2
  81         select SUPPORT_CPU_UCODE_IN_CBFS
  82         select TSC_MONOTONIC_TIMER
  83         select UDELAY_TSC
  84         select UDK_2017_BINDING
  85         select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
  86         select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
  87         select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
  88         select SOC_INTEL_COMMON_BASECODE
  89         select SOC_INTEL_COMMON_BASECODE_RAMTOP
  90         select CR50_USE_LONG_INTERRUPT_PULSES if TPM_GOOGLE_CR50
  91         select X86_CLFLUSH_CAR
  92         help
  93           Intel Tigerlake support
  94
  95 config SOC_INTEL_TIGERLAKE_PCH_H
  96         bool
  97
  98 if SOC_INTEL_TIGERLAKE
  99
 100 config MAX_CPUS
 101         int
 102         default 16 if SOC_INTEL_TIGERLAKE_PCH_H
 103         default 8
 104
 105 config DIMM_SPD_SIZE
 106         default 512
 107
 108 config DCACHE_RAM_BASE
 109         default 0xfef00000
 110
 111 config DCACHE_RAM_SIZE
 112         default 0x80000
 113         help
 114           The size of the cache-as-ram region required during bootblock
 115           and/or romstage.
 116
 117 config DCACHE_BSP_STACK_SIZE
 118         hex
 119         default 0x40400
 120         help
 121           The amount of anticipated stack usage in CAR by bootblock and
 122           other stages. In the case of FSP_USES_CB_STACK default value will be
 123           sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement
 124           (~1KiB).
 125
 126 config FSP_TEMP_RAM_SIZE
 127         hex
 128         default 0x20000
 129         help
 130           The amount of anticipated heap usage in CAR by FSP.
 131           Refer to Platform FSP integration guide document to know
 132           the exact FSP requirement for Heap setup.
 133
 134 config CHIPSET_DEVICETREE
 135         string
 136         default "soc/intel/tigerlake/chipset_pch_h.cb" if SOC_INTEL_TIGERLAKE_PCH_H
 137         default "soc/intel/tigerlake/chipset.cb"
 138
 139 config EXT_BIOS_WIN_BASE
 140         default 0xf8000000
 141
 142 config EXT_BIOS_WIN_SIZE
 143         default 0x2000000
 144
 145 config IFD_CHIPSET
 146         string
 147         default "tgl"
 148
 149 config IED_REGION_SIZE
 150         hex
 151         default 0x400000
 152
 153 config INTEL_TME
 154         default n
 155
 156 config MAX_ROOT_PORTS
 157         int
 158         default 24 if SOC_INTEL_TIGERLAKE_PCH_H
 159         default 12
 160
 161 config MAX_PCIE_CLOCK_SRC
 162         int
 163         default 16 if SOC_INTEL_TIGERLAKE_PCH_H
 164         default 7
 165
 166 config SMM_TSEG_SIZE
 167         hex
 168         default 0x800000
 169
 170 config SMM_RESERVED_SIZE
 171         hex
 172         default 0x200000
 173
 174 config PCR_BASE_ADDRESS
 175         hex
 176         default 0xfd000000
 177         help
 178           This option allows you to select MMIO Base Address of sideband bus.
 179
 180 config ECAM_MMCONF_BASE_ADDRESS
 181         default 0xc0000000
 182
 183 config CPU_BCLK_MHZ
 184         int
 185         default 100
 186
 187 config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 188         int
 189         default 120
 190
 191 config CPU_XTAL_HZ
 192         default 38400000
 193
 194 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 195         int
 196         default 133
 197
 198 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 199         int
 200         default 4
 201
 202 config SOC_INTEL_I2C_DEV_MAX
 203         int
 204         default 6
 205
 206 config SOC_INTEL_UART_DEV_MAX
 207         int
 208         default 3
 209
 210 config CONSOLE_UART_BASE_ADDRESS
 211         hex
 212         default 0xfe03e000
 213         depends on INTEL_LPSS_UART_FOR_CONSOLE
 214
 215 # Clock divider parameters for 115200 baud rate
 216 # Baudrate = (UART source clock * M) /(N *16)
 217 # TGL UART source clock: 100MHz
 218 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
 219         hex
 220         default 0x25a
 221
 222 config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 223         hex
 224         default 0x7fff
 225
 226 config VBOOT
 227         select VBOOT_MUST_REQUEST_DISPLAY
 228         select VBOOT_STARTS_IN_BOOTBLOCK
 229         select VBOOT_VBNV_CMOS
 230         select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
 231
 232 config CBFS_SIZE
 233         default 0x200000
 234
 235 config FSP_TYPE_IOT
 236         bool
 237         default n
 238         help
 239           This option allows to select FSP IOT type from 3rdparty/fsp repo
 240
 241 config FSP_TYPE_CLIENT
 242         bool
 243         default !FSP_TYPE_IOT
 244         help
 245           This option allows to select FSP CLIENT type from 3rdparty/fsp repo
 246
 247 config FSP_HEADER_PATH
 248         default "3rdparty/fsp/TigerLakeFspBinPkg/TGL_IOT/Include/" if FSP_TYPE_IOT
 249         default "3rdparty/fsp/TigerLakeFspBinPkg/Client/Include/" if FSP_TYPE_CLIENT
 250
 251 config FSP_FD_PATH
 252         default "3rdparty/fsp/TigerLakeFspBinPkg/TGL_IOT/Fsp.fd" if FSP_TYPE_IOT
 253         default "3rdparty/fsp/TigerLakeFspBinPkg/Client/Fsp.fd" if FSP_TYPE_CLIENT
 254
 255 config PRERAM_CBMEM_CONSOLE_SIZE
 256         hex
 257         default 0x2000
 258
 259 config DATA_BUS_WIDTH
 260         int
 261         default 128
 262
 263 config DIMMS_PER_CHANNEL
 264         int
 265         default 2
 266
 267 config MRC_CHANNEL_WIDTH
 268         int
 269         default 16
 270
 271 # Intel recommends reserving the following resources per USB4 root port,
 272 # from TGL BIOS Spec (doc #611569) Revision 0.7.6 Section 7.2.5.1.5
 273 # - 42 buses
 274 # - 194 MiB Non-prefetchable memory
 275 # - 448 MiB Prefetchable memory
 276 if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 277
 278 config PCIEXP_HOTPLUG_BUSES
 279         default 42
 280
 281 config PCIEXP_HOTPLUG_MEM
 282         default 0xc200000  # 194 MiB
 283
 284 config PCIEXP_HOTPLUG_PREFETCH_MEM
 285         default 0x1c000000 # 448 MiB
 286
 287 endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 288
 289 config INTEL_GMA_BCLV_OFFSET
 290         default 0xc8258
 291
 292 config INTEL_GMA_BCLV_WIDTH
 293         default 32
 294
 295 config INTEL_GMA_BCLM_OFFSET
 296         default 0xc8254
 297
 298 config INTEL_GMA_BCLM_WIDTH
 299         default 32
 300
 301 endif