1 /* SPDX-License-Identifier: GPL-2.0-only */
6 #include <drivers/i2c/designware/dw_i2c.h>
7 #include <drivers/intel/gma/gma.h>
9 #include <intelblocks/cfg.h>
10 #include <intelblocks/gspi.h>
11 #include <intelblocks/lpc_lib.h>
12 #include <intelblocks/pcie_rp.h>
13 #include <intelblocks/power_limit.h>
14 #include <intelblocks/tcss.h>
17 #include <soc/pci_devs.h>
19 #include <soc/serialio.h>
23 #define MAX_HD_AUDIO_DMIC_LINKS 2
24 #define MAX_HD_AUDIO_SNDW_LINKS 4
25 #define MAX_HD_AUDIO_SSP_LINKS 6
27 /* Define config parameters for In-Band ECC (IBECC). */
28 #define MAX_IBECC_REGIONS 8
40 bool region_enable
[MAX_IBECC_REGIONS
];
41 uint16_t region_base
[MAX_IBECC_REGIONS
];
42 uint16_t region_mask
[MAX_IBECC_REGIONS
];
45 /* The first two are for TGL-U */
46 enum soc_intel_tigerlake_power_limits
{
47 POWER_LIMITS_U_2_CORE
,
48 POWER_LIMITS_U_4_CORE
,
49 POWER_LIMITS_Y_2_CORE
,
50 POWER_LIMITS_Y_4_CORE
,
51 POWER_LIMITS_H_6_CORE
,
52 POWER_LIMITS_H_8_CORE
,
57 * Enable External V1P05 Rail in: BIT0:S0i1/S0i2,
58 * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5
60 enum fivr_enable_states
{
61 FIVR_ENABLE_S0i1_S0i2
= BIT(0),
62 FIVR_ENABLE_S0i3
= BIT(1),
63 FIVR_ENABLE_S3
= BIT(2),
64 FIVR_ENABLE_S4
= BIT(3),
65 FIVR_ENABLE_S5
= BIT(4),
69 * Enable the following for External V1p05 rail
70 * BIT1: Normal Active voltage supported
71 * BIT2: Minimum active voltage supported
72 * BIT3: Minimum Retention voltage supported
74 enum fivr_voltage_supported
{
75 FIVR_VOLTAGE_NORMAL
= BIT(1),
76 FIVR_VOLTAGE_MIN_ACTIVE
= BIT(2),
77 FIVR_VOLTAGE_MIN_RETENTION
= BIT(3),
80 #define FIVR_ENABLE_ALL_SX (FIVR_ENABLE_S0i1_S0i2 | FIVR_ENABLE_S0i3 | \
81 FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5)
83 /* Bit values for use in LpmStateEnableMask. */
93 LPM_S0iX_ALL
= LPM_S0i2_0
| LPM_S0i2_1
| LPM_S0i2_2
94 | LPM_S0i3_0
| LPM_S0i3_1
| LPM_S0i3_2
| LPM_S0i3_3
| LPM_S0i3_4
,
98 * Slew Rate configuration for Deep Package C States for VR domain.
99 * They are fast time divided by 2.
112 enum ddi_port_config
{
113 DDI_PORT_CFG_NO_LFP
= 0,
114 DDI_PORT_CFG_EDP
= 1,
115 DDI_PORT_CFG_MIPI_DSI
= 2,
118 struct soc_intel_tigerlake_config
{
119 /* Common struct containing soc config data required by common code */
120 struct soc_intel_common_config common_soc_config
;
122 /* Common struct containing power limits configuration information */
123 struct soc_power_limits_config power_limits_config
[POWER_LIMITS_MAX
];
125 /* Configuration for boot TDP selection; */
126 uint8_t ConfigTdpLevel
;
128 /* Gpio group routed to each dword of the GPE0 block. Values are
129 * of the form PMC_GPP_[A:U] or GPD. */
130 uint8_t pmc_gpe0_dw0
; /* GPE0_31_0 STS/EN */
131 uint8_t pmc_gpe0_dw1
; /* GPE0_63_32 STS/EN */
132 uint8_t pmc_gpe0_dw2
; /* GPE0_95_64 STS/EN */
134 /* LPC fixed enables and ranges */
137 /* Generic IO decode ranges */
143 /* Enable S0iX support */
145 /* S0iX: Selectively disable individual sub-states, by default all are enabled. */
146 enum lpm_state_mask LpmStateDisableMask
;
148 /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
149 uint8_t TcssD3HotDisable
;
151 /* Enable DPTF support */
154 /* Deep SX enable for both AC and DC */
155 int deep_s3_enable_ac
;
156 int deep_s3_enable_dc
;
157 int deep_s5_enable_ac
;
158 int deep_s5_enable_dc
;
160 /* Deep Sx Configuration
161 * DSX_EN_WAKE_PIN - Enable WAKE# pin
162 * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin
163 * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */
164 uint32_t deep_sx_config
;
166 /* TCC activation offset */
169 /* In-Band ECC (IBECC) configuration */
170 struct ibecc_config ibecc
;
172 /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
173 * When enabled memory will be training at two different frequencies.
174 * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2,
175 * 4:FixedPoint3, 5:Enabled */
185 /* Rank Margin Tool. 1:Enable, 0:Disable */
188 /* Command Pins Mirrored */
192 struct usb2_port_config usb2_ports
[16];
193 struct usb3_port_config usb3_ports
[10];
194 /* Wake Enable Bitmap for USB2 ports */
195 uint16_t usb2_wake_enable_bitmap
;
196 /* Wake Enable Bitmap for USB3 ports */
197 uint16_t usb3_wake_enable_bitmap
;
198 /* PCH USB2 PHY Power Gating disable */
199 uint8_t usb2_phy_sus_pg_disable
;
200 /* Program OC pins for TCSS */
201 struct tcss_port_config tcss_ports
[MAX_TYPE_C_PORTS
];
204 * Acoustic Noise Mitigation
206 * 1 - Enable noise mitigation
208 uint8_t AcousticNoiseMitigation
;
211 * Offset 0x054B - Disable Fast Slew Rate for Deep Package
212 * C States for VCCin in VR domain. Disable Fast Slew Rate
213 * for Deep Package C States based on Acoustic Noise
214 * Mitigation feature enabled.
218 uint8_t FastPkgCRampDisable
;
221 * Offset 0x0550 - Slew Rate configuration for Deep Package
222 * C States for VCCin in VR domain. Slew Rate configuration
223 * for Deep Package C States for VR domain based on Acoustic
224 * Noise Mitigation feature enabled.
226 uint8_t SlowSlewRate
;
230 uint8_t SataSalpSupport
;
231 uint8_t SataPortsEnable
[8];
232 uint8_t SataPortsDevSlp
[8];
235 * Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
236 * Default 0. Setting this to 1 disables the SATA Power Optimizer.
238 uint8_t SataPwrOptimizeDisable
;
241 * SATA Port Enable Dito Config.
242 * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
244 uint8_t SataPortsEnableDitoConfig
[8];
246 /* SataPortsDmVal is the DITO multiplier. Default is 15. */
247 uint8_t SataPortsDmVal
[8];
248 /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */
249 uint16_t SataPortsDitoVal
[8];
252 uint8_t PchHdaDspEnable
;
253 uint8_t PchHdaAudioLinkHdaEnable
;
254 uint8_t PchHdaAudioLinkDmicEnable
[MAX_HD_AUDIO_DMIC_LINKS
];
255 uint8_t PchHdaAudioLinkSspEnable
[MAX_HD_AUDIO_SSP_LINKS
];
256 uint8_t PchHdaAudioLinkSndwEnable
[MAX_HD_AUDIO_SNDW_LINKS
];
257 uint8_t PchHdaIDispCodecDisconnect
;
259 /* PCIe Root Ports */
260 uint8_t PcieRpHotPlug
[CONFIG_MAX_ROOT_PORTS
];
261 /* Implemented as slot or built-in? */
262 uint8_t PcieRpSlotImplemented
[CONFIG_MAX_ROOT_PORTS
];
263 /* PCIe output clocks type to PCIe devices.
264 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
266 uint8_t PcieClkSrcUsage
[CONFIG_MAX_PCIE_CLOCK_SRC
];
267 /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
269 uint8_t PcieClkSrcClkReq
[CONFIG_MAX_PCIE_CLOCK_SRC
];
271 /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
272 uint8_t PcieRpClkReqDetect
[CONFIG_MAX_ROOT_PORTS
];
274 /* Enable PCIe Precision Time Measurement for Root Ports (disabled by default) */
275 uint8_t PciePtm
[CONFIG_MAX_ROOT_PORTS
];
277 /* PCIe RP L1 substate */
278 enum L1_substates_control PcieRpL1Substates
[CONFIG_MAX_ROOT_PORTS
];
280 /* PCIe LTR: Enable (1) / Disable (0) */
281 uint8_t PcieRpLtrEnable
[CONFIG_MAX_ROOT_PORTS
];
283 /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
284 uint8_t PcieRpAdvancedErrorReporting
[CONFIG_MAX_ROOT_PORTS
];
287 uint8_t SkipExtGfxScan
;
294 * SerialIO device mode selection:
295 * PchSerialIoDisabled,
298 * PchSerialIoLegacyUart,
299 * PchSerialIoSkipInit
301 uint8_t SerialIoI2cMode
[CONFIG_SOC_INTEL_I2C_DEV_MAX
];
302 uint8_t SerialIoGSpiMode
[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX
];
303 uint8_t SerialIoUartMode
[CONFIG_SOC_INTEL_UART_DEV_MAX
];
305 * GSPIn Default Chip Select Mode:
309 uint8_t SerialIoGSpiCsMode
[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX
];
311 * GSPIn Default Chip Select State:
315 uint8_t SerialIoGSpiCsState
[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX
];
318 * TraceHubMode config
319 * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
321 uint8_t TraceHubMode
;
323 /* Debug interface selection */
325 DEBUG_INTERFACE_RAM
= (1 << 0),
326 DEBUG_INTERFACE_UART_8250IO
= (1 << 1),
327 DEBUG_INTERFACE_USB3
= (1 << 3),
328 DEBUG_INTERFACE_LPSS_SERIAL_IO
= (1 << 4),
329 DEBUG_INTERFACE_TRACEHUB
= (1 << 5),
330 } debug_interface_flag
;
332 /* CNVi BT Core Enable/Disable */
335 /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
336 bool CnviBtAudioOffload
;
343 * Specifies which Type-C Ports are enabled on the system
344 * each bit represents a port starting at 0
345 * Example: set value to 0x3 for ports 0 and 1 to be enabled
350 * These GPIOs will be programmed by the IOM to handle biasing of the
351 * Type-C aux (SBU) signals when certain alternate modes are used.
352 * `pad_auxn_dc` should be assigned to the GPIO pad providing negative
353 * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly,
354 * `pad_auxp_dc` should be assigned to the GPIO providing positive bias
355 * (name often contains `AUXP_DC` or `_AUX_P`).
357 struct typec_aux_bias_pads typec_aux_bias_pads
[MAX_TYPE_C_PORTS
];
360 * SOC Aux orientation override:
361 * This is a bitfield that corresponds to up to 4 TCSS ports on TGL.
362 * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC.
363 * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines
364 * on the motherboard.
368 /* Connect Topology Command timeout value */
369 uint16_t ITbtConnectTopologyTimeoutInMs
;
372 * Override GPIO PM configuration:
373 * 0: Use FSP default GPIO PM program,
374 * 1: coreboot to override GPIO PM program
376 uint8_t gpio_override_pm
;
379 * GPIO PM configuration: 0 to disable, 1 to enable power gating
381 * Bit 5: MISCCFG_GPSIDEDPCGEN
382 * Bit 4: MISCCFG_GPRCOMPCDLCGEN
383 * Bit 3: MISCCFG_GPRTCDLCGEN
384 * Bit 2: MISCCFG_GSXLCGEN
385 * Bit 1: MISCCFG_GPDPCGEN
386 * Bit 0: MISCCFG_GPDLCGEN
388 uint8_t gpio_pm
[TOTAL_GPIO_COMM
];
390 /* DDI port config */
391 enum ddi_port_config DdiPortAConfig
;
392 enum ddi_port_config DdiPortBConfig
;
394 /* Enable(1)/Disable(0) HPD */
403 /* Enable(1)/Disable(0) DDC */
412 /* Hybrid storage mode enable (1) / disable (0)
413 * This mode makes FSP detect Optane and NVME and set PCIe lane mode
415 uint8_t HybridStorageMode
;
418 * Override CPU flex ratio value:
419 * CPU ratio value controls the maximum processor non-turbo ratio.
420 * Valid Range 0 to 63.
421 * In general descriptor provides option to set default cpu flex ratio.
422 * Default cpu flex ratio 0 ensures booting with non-turbo max frequency.
423 * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
424 * Only override CPU flex ratio to not boot with non-turbo max.
426 uint8_t cpu_ratio_override
;
429 * Enable(0)/Disable(1) DMI Power Optimizer on PCH side.
430 * Default 0. Setting this to 1 disables the DMI Power Optimizer.
432 uint8_t DmiPwrOptimizeDisable
;
434 /* structure containing various settings for PCH FIVRs */
436 bool configure_ext_fivr
;
437 enum fivr_enable_states v1p05_enable_bitmap
;
438 enum fivr_enable_states vnn_enable_bitmap
;
439 enum fivr_voltage_supported v1p05_supported_voltage_bitmap
;
440 enum fivr_voltage_supported vnn_supported_voltage_bitmap
;
441 /* External Icc Max for V1p05 rail in mA */
442 int v1p05_icc_max_ma
;
443 /* External Vnn Voltage in mV */
444 int vnn_sx_voltage_mv
;
448 * Enable(1)/Disable(0) CPU Replacement check.
449 * Default 0. Setting this to 1 to check CPU replacement.
451 uint8_t CpuReplacementCheck
;
454 * SLP_S3 Minimum Assertion Width Policy
460 uint8_t PchPmSlpS3MinAssert
;
463 * SLP_S4 Minimum Assertion Width Policy
469 uint8_t PchPmSlpS4MinAssert
;
472 * SLP_SUS Minimum Assertion Width Policy
478 uint8_t PchPmSlpSusMinAssert
;
481 * SLP_A Minimum Assertion Width Policy
487 uint8_t PchPmSlpAMinAssert
;
490 * PCH PM Reset Power Cycle Duration
497 * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the
498 * stretch duration programmed in the following registers:
499 * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
500 * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
501 * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
502 * - PM_CFG.SLP_LAN_MIN_ASST_WDTH
504 uint8_t PchPmPwrCycDur
;
505 bool external_clk_gated
;
506 bool external_phy_gated
;
507 bool external_bypass
;
509 /* i915 struct for GMA backlight control */
510 struct i915_gpu_controller_info gfx
;
513 typedef struct soc_intel_tigerlake_config config_t
;