src/soc/intel/tigerlake/fsp_params.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <assert.h>
   4 #include <console/console.h>
   5 #include <cpu/intel/cpu_ids.h>
   6 #include <device/device.h>
   7 #include <device/pci_ops.h>
   8 #include <device/pci.h>
   9 #include <device/pci_ids.h>
  10 #include <drivers/usb/acpi/chip.h>
  11 #include <fsp/api.h>
  12 #include <fsp/ppi/mp_service_ppi.h>
  13 #include <fsp/util.h>
  14 #include <gpio.h>
  15 #include <intelblocks/cse.h>
  16 #include <intelblocks/irq.h>
  17 #include <intelblocks/lpss.h>
  18 #include <intelblocks/pmclib.h>
  19 #include <intelblocks/tcss.h>
  20 #include <intelblocks/xdci.h>
  21 #include <intelpch/lockdown.h>
  22 #include <option.h>
  23 #include <security/vboot/vboot_common.h>
  24 #include <soc/intel/common/vbt.h>
  25 #include <soc/lpm.h>
  26 #include <soc/pci_devs.h>
  27 #include <soc/ramstage.h>
  28 #include <soc/soc_chip.h>
  29 #include <soc/tcss.h>
  30 #include <static.h>
  31 #include <string.h>
  32 #include <types.h>
  33
  34 /* THC assignment definition */
  35 #define THC_NONE        0
  36 #define THC_0           1
  37 #define THC_1           2
  38
  39 /* SATA DEVSLP idle timeout default values */
  40 #define DEF_DMVAL       15
  41 #define DEF_DITOVAL     625
  42
  43 /*
  44  * ME End of Post configuration
  45  * 0 - Disable EOP.
  46  * 1 - Send in PEI (Applicable for FSP in API mode)
  47  * 2 - Send in DXE (Not applicable for FSP in API mode)
  48  */
  49 enum {
  50         EOP_DISABLE = 0,
  51         EOP_PEI = 1,
  52         EOP_DXE = 2,
  53 };
  54
  55 /*
  56  * Chip config parameter PcieRpL1Substates uses (UPD value + 1)
  57  * because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
  58  * In order to ensure that mainboard setting does not disable L1 substates
  59  * incorrectly, chip config parameter values are offset by 1 with 0 meaning
  60  * use FSP UPD default. get_l1_substate_control() ensures that the right UPD
  61  * value is set in fsp_params.
  62  * 0: Use FSP UPD default
  63  * 1: Disable L1 substates
  64  * 2: Use L1.1
  65  * 3: Use L1.2 (FSP UPD default)
  66  */
  67 static int get_l1_substate_control(enum L1_substates_control ctl)
  68 {
  69         if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
  70                 ctl = L1_SS_L1_2;
  71         return ctl - 1;
  72 }
  73
  74 static void parse_devicetree(FSP_S_CONFIG *params)
  75 {
  76         const struct soc_intel_tigerlake_config *config;
  77         config = config_of_soc();
  78
  79         for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
  80                 params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
  81
  82         for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
  83                 params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
  84                 params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i];
  85                 params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i];
  86         }
  87
  88         for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++)
  89                 params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
  90 }
  91
  92 /*
  93  * The FSP expects a certain list of PCI devices to be in the DevIntConfig table,
  94  * regardless of whether or not they are used by the mainboard.
  95  */
  96 static const struct slot_irq_constraints irq_constraints[] = {
  97         {
  98                 .slot = SA_DEV_SLOT_PEG,
  99                 .fns = {
 100                         FIXED_INT_PIRQ(SA_DEVFN_PEG1, PCI_INT_A, PIRQ_A),
 101                         FIXED_INT_PIRQ(SA_DEVFN_PEG2, PCI_INT_B, PIRQ_B),
 102                         FIXED_INT_PIRQ(SA_DEVFN_PEG3, PCI_INT_C, PIRQ_C),
 103                 },
 104         },
 105         {
 106                 .slot = SA_DEV_SLOT_IGD,
 107                 .fns = {
 108                         ANY_PIRQ(SA_DEVFN_IGD),
 109                 },
 110         },
 111         {
 112                 .slot = SA_DEV_SLOT_DPTF,
 113                 .fns = {
 114                         ANY_PIRQ(SA_DEVFN_DPTF),
 115                 },
 116         },
 117         {
 118                 .slot = SA_DEV_SLOT_IPU,
 119                 .fns = {
 120                         ANY_PIRQ(SA_DEVFN_IPU),
 121                 },
 122         },
 123         {
 124                 .slot = SA_DEV_SLOT_CPU_PCIE,
 125                 .fns = {
 126                         FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE, PCI_INT_D, PIRQ_D),
 127                 },
 128         },
 129         {
 130                 .slot = SA_DEV_SLOT_TBT,
 131                 .fns = {
 132                         FIXED_INT_ANY_PIRQ(SA_DEVFN_TBT0, PCI_INT_A),
 133                         FIXED_INT_ANY_PIRQ(SA_DEVFN_TBT1, PCI_INT_B),
 134                         FIXED_INT_ANY_PIRQ(SA_DEVFN_TBT2, PCI_INT_C),
 135                         FIXED_INT_ANY_PIRQ(SA_DEVFN_TBT3, PCI_INT_D),
 136                 },
 137         },
 138         {
 139                 .slot = SA_DEV_SLOT_TCSS,
 140                 .fns = {
 141                         ANY_PIRQ(SA_DEVFN_TCSS_XHCI),
 142                         ANY_PIRQ(SA_DEVFN_TCSS_DMA0),
 143                         ANY_PIRQ(SA_DEVFN_TCSS_DMA1),
 144                 },
 145         },
 146         {
 147                 .slot = PCH_DEV_SLOT_SIO0,
 148                 .fns = {
 149                         ANY_PIRQ(PCH_DEVFN_CT),
 150                         ANY_PIRQ(PCH_DEVFN_THC0),
 151                         ANY_PIRQ(PCH_DEVFN_THC1),
 152                 },
 153         },
 154         {
 155                 .slot = PCH_DEV_SLOT_SIO1,
 156                 .fns = {
 157                         DIRECT_IRQ(PCH_DEVFN_UART3),
 158                 },
 159         },
 160         {
 161                 .slot = PCH_DEV_SLOT_ISH,
 162                 .fns = {
 163                         DIRECT_IRQ(PCH_DEVFN_ISH),
 164                         DIRECT_IRQ(PCH_DEVFN_GSPI2),
 165                 },
 166         },
 167         {
 168                 .slot = PCH_DEV_SLOT_SIO2,
 169                 .fns = {
 170                         DIRECT_IRQ(PCH_DEVFN_GSPI3),
 171                 },
 172         },
 173         {
 174                 .slot = PCH_DEV_SLOT_XHCI,
 175                 .fns = {
 176                         ANY_PIRQ(PCH_DEVFN_XHCI),
 177                         DIRECT_IRQ(PCH_DEVFN_USBOTG),
 178                         FIXED_INT_ANY_PIRQ(PCH_DEVFN_CNVI_WIFI, PCI_INT_A),
 179                 },
 180         },
 181         {
 182                 .slot = PCH_DEV_SLOT_SIO3,
 183                 .fns = {
 184                         DIRECT_IRQ(PCH_DEVFN_I2C0),
 185                         DIRECT_IRQ(PCH_DEVFN_I2C1),
 186                         DIRECT_IRQ(PCH_DEVFN_I2C2),
 187                         DIRECT_IRQ(PCH_DEVFN_I2C3),
 188                 },
 189         },
 190         {
 191                 .slot = PCH_DEV_SLOT_CSE,
 192                 .fns = {
 193                         ANY_PIRQ(PCH_DEVFN_CSE),
 194                         ANY_PIRQ(PCH_DEVFN_CSE_2),
 195                         ANY_PIRQ(PCH_DEVFN_CSE_IDER),
 196                         ANY_PIRQ(PCH_DEVFN_CSE_KT),
 197                         ANY_PIRQ(PCH_DEVFN_CSE_3),
 198                         ANY_PIRQ(PCH_DEVFN_CSE_4),
 199                 },
 200         },
 201         {
 202                 .slot = PCH_DEV_SLOT_SATA,
 203                 .fns = {
 204                         ANY_PIRQ(PCH_DEVFN_SATA),
 205                 },
 206         },
 207         {
 208                 .slot = PCH_DEV_SLOT_SIO4,
 209                 .fns = {
 210                         DIRECT_IRQ(PCH_DEVFN_I2C4),
 211                         DIRECT_IRQ(PCH_DEVFN_I2C5),
 212                         DIRECT_IRQ(PCH_DEVFN_UART2),
 213                 },
 214         },
 215         {
 216                 .slot = PCH_DEV_SLOT_PCIE,
 217                 .fns = {
 218                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A),
 219                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B),
 220                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C),
 221                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D),
 222                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A),
 223                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B),
 224                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C),
 225                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D),
 226                 },
 227         },
 228         {
 229                 .slot = PCH_DEV_SLOT_PCIE_1,
 230                 .fns = {
 231                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE9,  PCI_INT_A, PIRQ_A),
 232                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B),
 233                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C),
 234                         FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D),
 235                 },
 236         },
 237         {
 238                 .slot = PCH_DEV_SLOT_SIO5,
 239                 .fns = {
 240                         FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A),
 241                         FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B),
 242                         DIRECT_IRQ(PCH_DEVFN_GSPI0),
 243                         DIRECT_IRQ(PCH_DEVFN_GSPI1),
 244                 },
 245         },
 246         {
 247                 .slot = PCH_DEV_SLOT_ESPI,
 248                 .fns = {
 249                         ANY_PIRQ(PCH_DEVFN_HDA),
 250                         ANY_PIRQ(PCH_DEVFN_SMBUS),
 251                         ANY_PIRQ(PCH_DEVFN_GBE),
 252                         FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A),
 253                 },
 254         },
 255 };
 256
 257 __weak void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *config)
 258 {
 259         /* Override settings per board. */
 260 }
 261
 262 static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count)
 263 {
 264         const struct pci_irq_entry *entry = get_cached_pci_irqs();
 265         SI_PCH_DEVICE_INTERRUPT_CONFIG *config;
 266         size_t pch_total = 0;
 267         size_t cfg_count = 0;
 268
 269         if (!entry)
 270                 return NULL;
 271
 272         /* Count PCH devices */
 273         while (entry) {
 274                 if (is_pch_slot(entry->devfn))
 275                         ++pch_total;
 276                 entry = entry->next;
 277         }
 278
 279         /* Convert PCH device entries to FSP format */
 280         config = calloc(pch_total, sizeof(*config));
 281         entry = get_cached_pci_irqs();
 282         while (entry) {
 283                 if (!is_pch_slot(entry->devfn)) {
 284                         entry = entry->next;
 285                         continue;
 286                 }
 287
 288                 config[cfg_count].Device = PCI_SLOT(entry->devfn);
 289                 config[cfg_count].Function = PCI_FUNC(entry->devfn);
 290                 config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin;
 291                 config[cfg_count].Irq = entry->irq;
 292                 ++cfg_count;
 293
 294                 entry = entry->next;
 295         }
 296
 297         *out_count = cfg_count;
 298
 299         return config;
 300 }
 301
 302 /* UPD parameters to be initialized before SiliconInit */
 303 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 304 {
 305         int i;
 306         uint32_t cpu_id;
 307         FSP_S_CONFIG *params = &supd->FspsConfig;
 308         struct device *dev;
 309         struct soc_intel_tigerlake_config *config;
 310         config = config_of_soc();
 311         mainboard_update_soc_chip_config(config);
 312
 313         /* Parse device tree and enable/disable Serial I/O devices */
 314         parse_devicetree(params);
 315
 316         /* Load VBT before devicetree-specific config. */
 317         params->GraphicsConfigPtr = (uintptr_t)vbt_get();
 318
 319         /* Check if IGD is present and fill Graphics init param accordingly */
 320         params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
 321
 322         /* Use coreboot MP PPI services if Kconfig is enabled */
 323         if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
 324                 params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
 325
 326         /* D3Hot and D3Cold for TCSS */
 327         params->D3HotEnable = !config->TcssD3HotDisable;
 328         cpu_id = cpu_get_cpuid();
 329         if (cpu_id == CPUID_TIGERLAKE_A0)
 330                 params->D3ColdEnable = 0;
 331         else
 332                 params->D3ColdEnable = CONFIG(D3COLD_SUPPORT);
 333
 334         params->UsbTcPortEn = config->UsbTcPortEn;
 335         params->TcssAuxOri = config->TcssAuxOri;
 336
 337         /* Explicitly clear this field to avoid using defaults */
 338         memset(params->IomTypeCPortPadCfg, 0, sizeof(params->IomTypeCPortPadCfg));
 339
 340
 341         /* Assign PCI IRQs */
 342         if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints)))
 343                 die("ERROR: Unable to assign PCI IRQs, and no ACPI _PRT table is defined\n");
 344
 345         size_t pch_count = 0;
 346         const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count);
 347         params->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs);
 348         params->NumOfDevIntConfig = pch_count;
 349         printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n");
 350
 351         /*
 352          * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will
 353          * evaluate this UPD value and skip sending command. There will be no
 354          * delay for command completion.
 355          */
 356         params->ITbtConnectTopologyTimeoutInMs = 0;
 357
 358         /* Disable TcColdOnUsbConnect */
 359         params->DisableTccoldOnUsbConnected = 1;
 360
 361         /* Chipset Lockdown */
 362         const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP;
 363         params->PchLockDownGlobalSmi = lockdown_by_fsp;
 364         params->PchLockDownBiosInterface = lockdown_by_fsp;
 365         params->PchUnlockGpioPads = !lockdown_by_fsp;
 366         params->RtcMemoryLock = lockdown_by_fsp;
 367         params->SkipPamLock = !lockdown_by_fsp;
 368
 369         /* coreboot will send EOP before loading payload */
 370         params->EndOfPostMessage = EOP_DISABLE;
 371
 372         /* USB */
 373         for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
 374                 params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
 375                 params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
 376                 params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
 377                 params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
 378                 params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
 379
 380                 if (config->usb2_ports[i].enable)
 381                         params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
 382                 else
 383                         params->Usb2OverCurrentPin[i] = 0xff;
 384
 385                 if (config->usb2_ports[i].type_c)
 386                         params->PortResetMessageEnable[i] = 1;
 387         }
 388
 389         for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
 390                 params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
 391                 if (config->usb3_ports[i].enable) {
 392                         params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
 393                 } else {
 394                         params->Usb3OverCurrentPin[i] = 0xff;
 395                 }
 396                 if (config->usb3_ports[i].tx_de_emp) {
 397                         params->Usb3HsioTxDeEmphEnable[i] = 1;
 398                         params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
 399                 }
 400                 if (config->usb3_ports[i].tx_downscale_amp) {
 401                         params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
 402                         params->Usb3HsioTxDownscaleAmp[i] =
 403                                 config->usb3_ports[i].tx_downscale_amp;
 404                 }
 405         }
 406
 407         /* RP Configs */
 408         for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
 409                 params->PcieRpL1Substates[i] =
 410                         get_l1_substate_control(config->PcieRpL1Substates[i]);
 411                 params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i];
 412                 params->PcieRpAdvancedErrorReporting[i] =
 413                         config->PcieRpAdvancedErrorReporting[i];
 414                 params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
 415                 params->PciePtm[i] = config->PciePtm[i];
 416                 params->PcieRpSlotImplemented[i] = config->PcieRpSlotImplemented[i];
 417         }
 418
 419         /* Enable ClkReqDetect for enabled port */
 420         memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
 421                 sizeof(config->PcieRpClkReqDetect));
 422
 423         for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) {
 424                 if (config->tcss_ports[i].enable)
 425                         params->CpuUsb3OverCurrentPin[i] =
 426                                         config->tcss_ports[i].ocpin;
 427         }
 428
 429         params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG);
 430
 431         /* PCH UART selection for FSP Debug */
 432         params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
 433         ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE);
 434         params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
 435
 436         /* SATA */
 437         params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
 438         if (params->SataEnable) {
 439                 params->SataMode = config->SataMode;
 440                 params->SataSalpSupport = config->SataSalpSupport;
 441                 memcpy(params->SataPortsEnable, config->SataPortsEnable,
 442                         sizeof(params->SataPortsEnable));
 443                 memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
 444                         sizeof(params->SataPortsDevSlp));
 445         }
 446
 447         /* S0iX: Selectively enable individual sub-states,
 448          * by default all are enabled.
 449          *
 450          * LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
 451          * LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4
 452          */
 453         params->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask(config);
 454
 455         /*
 456          * Power Optimizer for DMI and SATA.
 457          * DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0.
 458          * Boards not needing the optimizers explicitly disables them by setting
 459          * these disable variables to 1 in devicetree overrides.
 460          */
 461         params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable);
 462         params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
 463
 464         /*
 465          *  Enable DEVSLP Idle Timeout settings DmVal and DitoVal.
 466          *  SataPortsDmVal is the DITO multiplier. Default is 15.
 467          *  SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms.
 468          *  The default values can be changed from devicetree.
 469          */
 470         for (i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) {
 471                 if (config->SataPortsEnableDitoConfig[i]) {
 472                         if (config->SataPortsDmVal[i])
 473                                 params->SataPortsDmVal[i] = config->SataPortsDmVal[i];
 474                         else
 475                                 params->SataPortsDmVal[i] = DEF_DMVAL;
 476
 477                         if (config->SataPortsDitoVal[i])
 478                                 params->SataPortsDitoVal[i] = config->SataPortsDitoVal[i];
 479                         else
 480                                 params->SataPortsDitoVal[i] = DEF_DITOVAL;
 481                 }
 482         }
 483
 484         params->AcousticNoiseMitigation = config->AcousticNoiseMitigation;
 485         params->FastPkgCRampDisable[0] = config->FastPkgCRampDisable;
 486         params->SlowSlewRate[0] = config->SlowSlewRate;
 487
 488         /* Enable TCPU for processor thermal control */
 489         params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF);
 490
 491         /* Set TccActivationOffset */
 492         params->TccActivationOffset = config->tcc_offset;
 493
 494         /* LAN */
 495         params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE);
 496
 497         /* CNVi */
 498         struct device *port = NULL;
 499         struct drivers_usb_acpi_config *usb_cfg = NULL;
 500         bool usb_audio_offload = false;
 501
 502         /* Search through the devicetree for matching USB devices */
 503         while ((port = dev_find_path(port, DEVICE_PATH_USB)) != NULL) {
 504                 /* Skip ports that are not enabled or not of USB type */
 505                 if (!port->enabled || port->path.type != DEVICE_PATH_USB)
 506                         continue;
 507
 508                 usb_cfg = port->chip_info;
 509                 if (usb_cfg && usb_cfg->cnvi_bt_audio_offload) {
 510                         usb_audio_offload = true;
 511                         break;
 512                 }
 513
 514         }
 515
 516         params->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI);
 517         params->CnviBtCore = config->CnviBtCore;
 518         params->CnviBtAudioOffload = config->CnviBtAudioOffload;
 519
 520         if (!params->CnviBtCore && params->CnviBtAudioOffload) {
 521                 printk(BIOS_ERR, "BT offload is enabled without CNVi BT being enabled\n");
 522                 params->CnviBtAudioOffload = 0;
 523         }
 524         if (!params->CnviMode && params->CnviBtCore) {
 525                 printk(BIOS_ERR, "CNVi BT is enabled without CNVi being enabled\n");
 526                 params->CnviBtCore = 0;
 527                 params->CnviBtAudioOffload = 0;
 528         }
 529         if (params->CnviBtAudioOffload && !usb_audio_offload) {
 530                 printk(BIOS_WARNING, "CNVi BT Audio offload enabled but not in USB driver.\n");
 531         }
 532         if (!params->CnviBtAudioOffload && usb_cfg && usb_audio_offload) {
 533                 printk(BIOS_ERR, "USB BT Audio offload enabled but CNVi BT offload disabled\n");
 534                 usb_cfg->cnvi_bt_audio_offload = 0;
 535         }
 536
 537         /* VMD */
 538         params->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD);
 539
 540         /* THC */
 541         params->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE;
 542         params->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE;
 543
 544         /* Legacy 8254 timer support */
 545         bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
 546         params->Enable8254ClockGating = !use_8254;
 547         params->Enable8254ClockGatingOnS3 = !use_8254;
 548
 549         /*
 550          * Legacy PM ACPI Timer (and TCO Timer)
 551          * This *must* be 1 in any case to keep FSP from
 552          *  1) enabling PM ACPI Timer emulation in uCode.
 553          *  2) disabling the PM ACPI Timer.
 554          * We handle both by ourself!
 555          */
 556         params->EnableTcoTimer = 1;
 557
 558         /* Enable Hybrid storage auto detection */
 559         if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && cse_is_hfs3_fw_sku_lite()
 560                 && vboot_recovery_mode_enabled() && !cse_is_hfs1_com_normal()) {
 561                 /*
 562                  * CSE Lite SKU does not support hybrid storage dynamic configuration
 563                  * in CSE RO boot, and FSP does not allow to send the strap override
 564                  * HECI commands if CSE is not in normal mode; hence, hybrid storage
 565                  * mode is disabled on CSE RO boot in recovery boot mode.
 566                  */
 567                 printk(BIOS_INFO, "cse_lite: CSE RO boot. HybridStorageMode disabled\n");
 568                 params->HybridStorageMode = 0;
 569         } else {
 570                 params->HybridStorageMode = config->HybridStorageMode;
 571         }
 572
 573         /* USB4/TBT */
 574         for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) {
 575                 dev = pcidev_on_root(SA_DEV_SLOT_TBT, i);
 576                 params->ITbtPcieRootPortEn[i] = is_dev_enabled(dev);
 577         }
 578
 579         /* PCH FIVR settings override */
 580         if (config->ext_fivr_settings.configure_ext_fivr) {
 581                 params->PchFivrExtV1p05RailEnabledStates =
 582                         config->ext_fivr_settings.v1p05_enable_bitmap;
 583
 584                 params->PchFivrExtV1p05RailSupportedVoltageStates =
 585                         config->ext_fivr_settings.v1p05_supported_voltage_bitmap;
 586
 587                 params->PchFivrExtVnnRailEnabledStates =
 588                         config->ext_fivr_settings.vnn_enable_bitmap;
 589
 590                 params->PchFivrExtVnnRailSupportedVoltageStates =
 591                         config->ext_fivr_settings.vnn_supported_voltage_bitmap;
 592
 593                 /* convert mV to number of 2.5 mV increments */
 594                 params->PchFivrExtVnnRailSxVoltage =
 595                         (config->ext_fivr_settings.vnn_sx_voltage_mv * 10) / 25;
 596
 597                 params->PchFivrExtV1p05RailIccMaximum =
 598                         config->ext_fivr_settings.v1p05_icc_max_ma;
 599         }
 600
 601         /* Apply minimum assertion width settings if non-zero */
 602         if (config->PchPmSlpS3MinAssert)
 603                 params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert;
 604         if (config->PchPmSlpS4MinAssert)
 605                 params->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert;
 606         if (config->PchPmSlpSusMinAssert)
 607                 params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert;
 608         if (config->PchPmSlpAMinAssert)
 609                 params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert;
 610
 611         /* Set Power Cycle Duration */
 612         if (config->PchPmPwrCycDur)
 613                 params->PchPmPwrCycDur = get_pm_pwr_cyc_dur(config->PchPmSlpS4MinAssert,
 614                                 config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert,
 615                                 config->PchPmPwrCycDur);
 616
 617         /* Override EnableMultiPhaseSiliconInit prior calling MultiPhaseSiInit */
 618         params->EnableMultiPhaseSiliconInit = fsp_is_multi_phase_init_enabled();
 619
 620         /* Disable C1 C-state Demotion */
 621         params->C1StateAutoDemotion = 0;
 622
 623         /* USB2 Phy Sus power gating setting override */
 624         params->PmcUsb2PhySusPgEnable = !config->usb2_phy_sus_pg_disable;
 625
 626         /*
 627          * Prevent FSP from programming write-once subsystem IDs by providing
 628          * a custom SSID table. Must have at least one entry for the FSP to
 629          * use the table.
 630          */
 631         struct svid_ssid_init_entry {
 632                 union {
 633                         struct {
 634                                 uint64_t reg:12;        /* Register offset */
 635                                 uint64_t function:3;
 636                                 uint64_t device:5;
 637                                 uint64_t bus:8;
 638                                 uint64_t :4;
 639                                 uint64_t segment:16;
 640                                 uint64_t :16;
 641                         };
 642                         uint64_t segbusdevfuncregister;
 643                 };
 644                 struct {
 645                         uint16_t svid;
 646                         uint16_t ssid;
 647                 };
 648                 uint32_t reserved;
 649         };
 650
 651         /*
 652          * The xHCI and HDA devices have RW/L rather than RW/O registers for
 653          * subsystem IDs and so must be written before FspSiliconInit locks
 654          * them with their default values.
 655          */
 656         const pci_devfn_t devfn_table[] = { PCH_DEVFN_XHCI, PCH_DEVFN_HDA };
 657         static struct svid_ssid_init_entry ssid_table[ARRAY_SIZE(devfn_table)];
 658
 659         for (i = 0; i < ARRAY_SIZE(devfn_table); i++) {
 660                 ssid_table[i].reg       = PCI_SUBSYSTEM_VENDOR_ID;
 661                 ssid_table[i].device    = PCI_SLOT(devfn_table[i]);
 662                 ssid_table[i].function  = PCI_FUNC(devfn_table[i]);
 663                 dev = pcidev_path_on_root(devfn_table[i]);
 664                 if (dev) {
 665                         ssid_table[i].svid = dev->subsystem_vendor;
 666                         ssid_table[i].ssid = dev->subsystem_device;
 667                 }
 668         }
 669
 670         params->SiSsidTablePtr = (uintptr_t)ssid_table;
 671         params->SiNumberOfSsidTableEntry = ARRAY_SIZE(ssid_table);
 672
 673         /*
 674          * Replace the default SVID:SSID value with the values specified in
 675          * the devicetree for the root device.
 676          */
 677         dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 678         params->SiCustomizedSvid = dev->subsystem_vendor;
 679         params->SiCustomizedSsid = dev->subsystem_device;
 680
 681         /* Ensure FSP will program the registers */
 682         params->SiSkipSsidProgramming = 0;
 683
 684         mainboard_silicon_init_params(params);
 685 }
 686
 687 /*
 688  * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit
 689  * This platform supports below MultiPhaseSIInit Phase(s):
 690  * Phase   |  FSP return point                                |  Purpose
 691  * ------- + ------------------------------------------------ + -------------------------------
 692  *   1     |  After TCSS initialization completed             |  for TCSS specific init
 693  */
 694 void platform_fsp_silicon_multi_phase_init_cb(uint32_t phase_index)
 695 {
 696         switch (phase_index) {
 697         case 1:
 698                 /* TCSS specific initialization here */
 699                 printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n",
 700                         __FILE__, __func__);
 701
 702                 if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) {
 703                         const config_t *config = config_of_soc();
 704                         tcss_configure(config->typec_aux_bias_pads);
 705                 }
 706                 break;
 707         default:
 708                 break;
 709         }
 710 }
 711
 712 /* Mainboard GPIO Configuration */
 713 __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 714 {
 715         printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 716 }