src/soc/intel/tigerlake/pmutil.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * Helper functions for dealing with power management registers
   5  * and the differences between PCH variants.
   6  */
   7
   8 /*
   9  * This file is created based on Intel Tiger Lake Processor PCH Datasheet
  10  * Document number: 575857
  11  * Chapter number: 4
  12  */
  13
  14 #define __SIMPLE_DEVICE__
  15
  16 #include <acpi/acpi_pm.h>
  17 #include <console/console.h>
  18 #include <device/mmio.h>
  19 #include <device/device.h>
  20 #include <device/pci.h>
  21 #include <gpio.h>
  22 #include <intelblocks/pmclib.h>
  23 #include <intelblocks/rtc.h>
  24 #include <intelblocks/tco.h>
  25 #include <intelpch/espi.h>
  26 #include <soc/gpe.h>
  27 #include <soc/iomap.h>
  28 #include <soc/pci_devs.h>
  29 #include <soc/pm.h>
  30 #include <soc/smbus.h>
  31 #include <soc/soc_chip.h>
  32 #include <security/vboot/vbnv.h>
  33 #include <static.h>
  34
  35 /*
  36  * SMI
  37  */
  38
  39 const char *const *soc_smi_sts_array(size_t *a)
  40 {
  41         static const char *const smi_sts_bits[] = {
  42                 [BIOS_STS_BIT] = "BIOS",
  43                 [LEGACY_USB_STS_BIT] = "LEGACY_USB",
  44                 [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
  45                 [APM_STS_BIT] = "APM",
  46                 [SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
  47                 [PM1_STS_BIT] = "PM1",
  48                 [GPE0_STS_BIT] = "GPE0",
  49                 [GPIO_STS_BIT] = "GPI",
  50                 [MCSMI_STS_BIT] = "MCSMI",
  51                 [DEVMON_STS_BIT] = "DEVMON",
  52                 [TCO_STS_BIT] = "TCO",
  53                 [PERIODIC_STS_BIT] = "PERIODIC",
  54                 [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",
  55                 [SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
  56                 [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
  57                 [MONITOR_STS_BIT] = "MONITOR",
  58                 [SPI_SMI_STS_BIT] = "SPI",
  59                 [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",
  60                 [ESPI_SMI_STS_BIT] = "ESPI_SMI",
  61         };
  62
  63         *a = ARRAY_SIZE(smi_sts_bits);
  64         return smi_sts_bits;
  65 }
  66
  67 /*
  68  * TCO
  69  */
  70
  71 const char *const *soc_tco_sts_array(size_t *a)
  72 {
  73         static const char *const tco_sts_bits[] = {
  74                 [0] = "NMI2SMI",
  75                 [1] = "SW_TCO",
  76                 [2] = "TCO_INT",
  77                 [3] = "TIMEOUT",
  78                 [7] = "NEWCENTURY",
  79                 [8] = "BIOSWR",
  80                 [9] = "DMISCI",
  81                 [10] = "DMISMI",
  82                 [12] = "DMISERR",
  83                 [13] = "SLVSEL",
  84                 [16] = "INTRD_DET",
  85                 [17] = "SECOND_TO",
  86                 [18] = "BOOT",
  87                 [20] = "SMLINK_SLV"
  88         };
  89
  90         *a = ARRAY_SIZE(tco_sts_bits);
  91         return tco_sts_bits;
  92 }
  93
  94 /*
  95  * GPE0
  96  */
  97
  98 const char *const *soc_std_gpe_sts_array(size_t *a)
  99 {
 100         static const char *const gpe_sts_bits[] = {
 101                 [1] = "HOTPLUG",
 102                 [2] = "SWGPE",
 103                 [6] = "TCO_SCI",
 104                 [7] = "SMB_WAK",
 105                 [9] = "PCI_EXP",
 106                 [10] = "BATLOW",
 107                 [11] = "PME",
 108                 [12] = "ME",
 109                 [13] = "PME_B0",
 110                 [14] = "eSPI",
 111                 [15] = "GPIO Tier-2",
 112                 [16] = "LAN_WAKE",
 113                 [18] = "WADT"
 114         };
 115
 116         *a = ARRAY_SIZE(gpe_sts_bits);
 117         return gpe_sts_bits;
 118 }
 119
 120 void pmc_set_disb(void)
 121 {
 122         /* Set the DISB after DRAM init */
 123         uint8_t disb_val;
 124         /* Only care about bits [23:16] of register GEN_PMCON_A */
 125         uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2);
 126
 127         disb_val = read8(addr);
 128         disb_val |= (DISB >> 16);
 129
 130         /* Don't clear bits that are write-1-to-clear */
 131         disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16);
 132         write8(addr, disb_val);
 133 }
 134
 135 /*
 136  * PMC controller gets hidden from PCI bus
 137  * during FSP-Silicon init call. Hence PWRMBASE
 138  * can't be accessible using PCI configuration space
 139  * read/write.
 140  */
 141 uint8_t *pmc_mmio_regs(void)
 142 {
 143         return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
 144 }
 145
 146 uintptr_t soc_read_pmc_base(void)
 147 {
 148         return (uintptr_t)pmc_mmio_regs();
 149 }
 150
 151 uint32_t *soc_pmc_etr_addr(void)
 152 {
 153         return (uint32_t *)(soc_read_pmc_base() + ETR);
 154 }
 155
 156 static void pmc_gpe0_different_values(const struct soc_intel_tigerlake_config *config)
 157 {
 158         bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) &&
 159                          (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) &&
 160                          (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2);
 161
 162         assert(result);
 163 }
 164
 165 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 166 {
 167         DEVTREE_CONST struct soc_intel_tigerlake_config *config;
 168
 169         config = config_of_soc();
 170
 171         pmc_gpe0_different_values(config);
 172
 173         /* Assign to out variable */
 174         *dw0 = config->pmc_gpe0_dw0;
 175         *dw1 = config->pmc_gpe0_dw1;
 176         *dw2 = config->pmc_gpe0_dw2;
 177 }
 178
 179 static int rtc_failed(uint32_t gen_pmcon_b)
 180 {
 181         return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
 182 }
 183
 184 static void clear_rtc_failed(void)
 185 {
 186         clrbits8(pmc_mmio_regs() + GEN_PMCON_B, RTC_BATTERY_DEAD);
 187 }
 188
 189 static int check_rtc_failed(uint32_t gen_pmcon_b)
 190 {
 191         const int failed = rtc_failed(gen_pmcon_b);
 192         if (failed) {
 193                 clear_rtc_failed();
 194                 printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", failed);
 195         }
 196
 197         return failed;
 198 }
 199
 200 int soc_get_rtc_failed(void)
 201 {
 202         const struct chipset_power_state *ps;
 203
 204         if (acpi_fetch_pm_state(&ps, PS_CLAIMER_RTC) < 0)
 205                 return 1;
 206
 207         return check_rtc_failed(ps->gen_pmcon_b);
 208 }
 209
 210 int vbnv_cmos_failed(void)
 211 {
 212         return check_rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
 213 }
 214
 215 static inline int deep_s3_enabled(void)
 216 {
 217         uint32_t deep_s3_pol;
 218
 219         deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
 220         return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
 221 }
 222
 223 /* Return 0, 3, or 5 to indicate the previous sleep state. */
 224 int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
 225 {
 226         /*
 227          * Check for any power failure to determine if this a wake from
 228          * S5 because the PCH does not set the WAK_STS bit when waking
 229          * from a true G3 state.
 230          */
 231         if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)))
 232                 prev_sleep_state = ACPI_S5;
 233
 234         /*
 235          * If waking from S3 determine if deep S3 is enabled. If not,
 236          * need to check both deep sleep well and normal suspend well.
 237          * Otherwise just check deep sleep well.
 238          */
 239         if (prev_sleep_state == ACPI_S3) {
 240                 /* PWR_FLR represents deep sleep power well loss. */
 241                 uint32_t mask = PWR_FLR;
 242
 243                 /* If deep s3 isn't enabled check the suspend well too. */
 244                 if (!deep_s3_enabled())
 245                         mask |= SUS_PWR_FLR;
 246
 247                 if (ps->gen_pmcon_a & mask)
 248                         prev_sleep_state = ACPI_S5;
 249         }
 250
 251         return prev_sleep_state;
 252 }
 253
 254 void soc_fill_power_state(struct chipset_power_state *ps)
 255 {
 256         uint8_t *pmc;
 257
 258         ps->tco1_sts = tco_read_reg(TCO1_STS);
 259         ps->tco2_sts = tco_read_reg(TCO2_STS);
 260
 261         printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
 262
 263         pmc = pmc_mmio_regs();
 264         ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
 265         ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
 266         ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
 267         ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
 268         ps->hpr_cause0 = read32(pmc + HPR_CAUSE0);
 269
 270         printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
 271                 ps->gen_pmcon_a, ps->gen_pmcon_b);
 272
 273         printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
 274                 ps->gblrst_cause[0], ps->gblrst_cause[1]);
 275
 276         printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0);
 277 }
 278
 279 /* STM Support */
 280 uint16_t get_pmbase(void)
 281 {
 282         return (uint16_t)ACPI_BASE_ADDRESS;
 283 }
 284
 285 /*
 286  * Set which power state system will be after reapplying
 287  * the power (from G3 State)
 288  */
 289 void pmc_soc_set_afterg3_en(const bool on)
 290 {
 291         uint8_t reg8;
 292         uint8_t *const pmcbase = pmc_mmio_regs();
 293
 294         reg8 = read8(pmcbase + GEN_PMCON_A);
 295         if (on)
 296                 reg8 &= ~SLEEP_AFTER_POWER_FAIL;
 297         else
 298                 reg8 |= SLEEP_AFTER_POWER_FAIL;
 299         write8(pmcbase + GEN_PMCON_A, reg8);
 300 }