src/soc/intel/xeon_sp/Kconfig

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 source "src/soc/intel/xeon_sp/*/Kconfig"
   4
   5 config XEON_SP_IBL
   6         bool
   7         default n
   8
   9 config XEON_SP_COMMON_BASE
  10         bool
  11         select ACPI_INTEL_HARDWARE_SLEEP_VALUES
  12         select ARCH_X86
  13         select BOOT_DEVICE_SUPPORTS_WRITES
  14         select CPU_INTEL_COMMON
  15         select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
  16         select FSP_CAR
  17         select FSP_M_XIP
  18         select FSP_COMPRESS_FSP_S_LZ4
  19         select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
  20         select FSP_T_XIP
  21         select HAVE_SMI_HANDLER
  22         select INTEL_CAR_NEM # For postcar only now
  23         select INTEL_DESCRIPTOR_MODE_CAPABLE
  24         select PARALLEL_MP_AP_WORK
  25         select PMC_GLOBAL_RESET_ENABLE_LOCK
  26         select POSTCAR_STAGE
  27         select REG_SCRIPT
  28         select SMM_TSEG
  29         select SOC_INTEL_COMMON
  30         select SOC_INTEL_COMMON_RESET
  31         select SOC_INTEL_COMMON_BLOCK
  32         select SOC_INTEL_COMMON_BLOCK_ACPI
  33         select SOC_INTEL_COMMON_BLOCK_CPU
  34         select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
  35         select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
  36         select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
  37         select SOC_INTEL_COMMON_BLOCK_SMM
  38         select SOC_INTEL_COMMON_BLOCK_TCO
  39         select SUPPORT_CPU_UCODE_IN_CBFS
  40         select SMM_PCI_RESOURCE_STORE
  41         select SOC_INTEL_COMMON_PCH_SERVER if !XEON_SP_IBL
  42         select SOC_INTEL_COMMON_IBL_BASE if XEON_SP_IBL
  43         select TSC_MONOTONIC_TIMER
  44         select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT
  45         select UDELAY_TSC
  46         select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
  47         select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
  48         select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
  49         select IDT_IN_EVERY_STAGE
  50
  51 if XEON_SP_COMMON_BASE
  52
  53 config MAX_SOCKET
  54         int
  55         default 2
  56
  57 config MAX_HECI_DEVICES
  58         int
  59         default 5
  60
  61 # For 2S config, the number of cpus could be as high as
  62 # 2 threads * 20 cores * 2 sockets
  63 config MAX_CPUS
  64         int
  65         default 80
  66
  67 config INTEL_ACPI_BASE_ADDRESS
  68         hex
  69         default 0x500
  70         help
  71           IO Address of ACPI.
  72
  73 config INTEL_PCH_PWRM_BASE_ADDRESS
  74         hex
  75         default 0xfe000000
  76         help
  77           PCH PWRM Base address.
  78
  79 config PCR_BASE_ADDRESS
  80         hex
  81         default 0xfd000000
  82         help
  83           This option allows you to select MMIO Base Address of sideband bus.
  84
  85 config DCACHE_BSP_STACK_SIZE
  86         hex
  87         default 0x10000
  88
  89 config ECAM_MMCONF_BASE_ADDRESS
  90         default 0x80000000
  91
  92 config ECAM_MMCONF_BUS_NUMBER
  93         default 512 if MAX_SOCKET = 4
  94         default 256
  95
  96 config ALWAYS_ALLOW_ABOVE_4G_ALLOCATION
  97         default y
  98
  99 config HPET_MIN_TICKS
 100         hex
 101         default 0x80
 102
 103 config SOC_INTEL_XEON_RAS
 104         bool
 105         select SOC_ACPI_HEST
 106         select SOC_RAS_ELOG
 107
 108 config HAVE_IOAT_DOMAINS
 109         bool
 110
 111 config SOC_INTEL_HAS_CXL
 112         bool
 113
 114 config SUPPORT_SIMICS_SIMULATION
 115         bool
 116         default y
 117         select SHADOW_ROM_TABLE_TO_EBDA
 118
 119 endif ## SOC_INTEL_XEON_SP