src/soc/intel/xeon_sp/acpi.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <acpi/acpigen.h>
   4 #include <acpi/acpigen_pci.h>
   5 #include <assert.h>
   6 #include <device/pci_ops.h>
   7 #include <intelblocks/acpi.h>
   8 #include <soc/chip_common.h>
   9 #include <soc/pci_devs.h>
  10 #include <soc/util.h>
  11 #include <southbridge/intel/common/acpi_pirq_gen.h>
  12 #include <static.h>
  13 #include <stdint.h>
  14 #include <stdio.h>
  15 #include <stdlib.h>
  16
  17 #include "chip.h"
  18
  19 /*
  20  * List of supported C-states in this processor.
  21  */
  22 enum {
  23         C_STATE_C1,     /* 0 */
  24         C_STATE_C3,     /* 1 */
  25         C_STATE_C6,     /* 2 */
  26         C_STATE_C7,     /* 3 */
  27         NUM_C_STATES
  28 };
  29
  30 static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
  31         [C_STATE_C1] = {
  32                 /* C1 */
  33                 .latency = 1,
  34                 .power = 0x3e8,
  35                 .resource = MWAIT_RES(0, 0),
  36         },
  37         [C_STATE_C3] = {
  38                 /* C3 */
  39                 .latency = 15,
  40                 .power = 0x1f4,
  41                 .resource = MWAIT_RES(1, 0),
  42         },
  43         [C_STATE_C6] = {
  44                 /* C6 */
  45                 .latency = 41,
  46                 .power = 0x15e,
  47                 .resource = MWAIT_RES(2, 0),
  48         },
  49         [C_STATE_C7] = {
  50                 /* C7 */
  51                 .latency = 41,
  52                 .power = 0x0c8,
  53                 .resource = MWAIT_RES(3, 0),
  54         }
  55 };
  56
  57 /* Max states supported */
  58 static int cstate_set_all[] = {
  59         C_STATE_C1,
  60         C_STATE_C3,
  61         C_STATE_C6,
  62         C_STATE_C7
  63 };
  64
  65 static int cstate_set_c1_c6[] = {
  66         C_STATE_C1,
  67         C_STATE_C6,
  68 };
  69
  70 const acpi_cstate_t *soc_get_cstate_map(size_t *entries)
  71 {
  72         static acpi_cstate_t map[ARRAY_SIZE(cstate_set_all)];
  73         int *cstate_set;
  74         int i;
  75
  76         const config_t *config = config_of_soc();
  77
  78         const enum acpi_cstate_mode states = config->cstate_states;
  79
  80         switch (states) {
  81         case CSTATES_C1C6:
  82                 *entries = ARRAY_SIZE(cstate_set_c1_c6);
  83                 cstate_set = cstate_set_c1_c6;
  84                 break;
  85         case CSTATES_ALL:
  86         default:
  87                 *entries = ARRAY_SIZE(cstate_set_all);
  88                 cstate_set = cstate_set_all;
  89                 break;
  90         }
  91
  92         for (i = 0; i < *entries; i++) {
  93                 map[i] = cstate_map[cstate_set[i]];
  94                 map[i].ctype = i + 1;
  95         }
  96         return map;
  97 }
  98
  99 void iio_domain_set_acpi_name(struct device *dev, const char *prefix)
 100 {
 101         const union xeon_domain_path dn = {
 102                 .domain_path = dev_get_domain_id(dev)
 103         };
 104
 105         assert(dn.socket < 8);
 106         assert(dn.stack < 32);
 107         assert(prefix != NULL && strlen(prefix) == 2);
 108
 109         if (dn.socket >= 8 || dn.stack >= 32 ||
 110             !prefix || strlen(prefix) != 2)
 111                 return;
 112
 113         char *name = xmalloc(ACPI_NAME_BUFFER_SIZE);
 114         snprintf(name, ACPI_NAME_BUFFER_SIZE, "%s%02X", prefix, ((dn.socket << 5) + dn.stack));
 115         dev->name = name;
 116 }
 117
 118 const char *soc_acpi_name(const struct device *dev)
 119 {
 120         if (dev->path.type == DEVICE_PATH_DOMAIN)
 121                 return dev->name;
 122
 123         /* FIXME: Add SoC specific device names here */
 124
 125         return NULL;
 126 }
 127
 128 void acpigen_write_OSC_pci_domain_fixed_caps(const struct device *domain,
 129                                 const uint32_t granted_pcie_features,
 130                                 const bool is_cxl_domain,
 131                                 const uint32_t granted_cxl_features)
 132 {
 133         acpigen_write_method("_OSC", 4);
 134
 135         acpigen_write_return_namestr("\\_SB.POSC");
 136         acpigen_emit_byte(ARG0_OP);
 137         acpigen_emit_byte(ARG1_OP);
 138         acpigen_emit_byte(ARG2_OP);
 139         acpigen_emit_byte(ARG3_OP);
 140         acpigen_write_integer(granted_pcie_features);
 141         acpigen_write_integer(is_cxl_domain);
 142         acpigen_write_integer(granted_cxl_features);
 143
 144         acpigen_pop_len();
 145 }
 146
 147 static bool read_physical_slot_number(const struct device *dev, uint8_t *psn)
 148 {
 149         if (!is_pci(dev))
 150                 return false;
 151
 152         const size_t pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
 153         if (!pos)
 154                 return false;
 155
 156         u32 sltcap = pci_read_config32(dev, pos + PCI_EXP_SLTCAP);
 157         *psn = ((sltcap >> 19) & 0x1FF);
 158         return true;
 159 }
 160
 161 static void acpigen_write_pci_root_port_devices(const struct device *rp)
 162 {
 163         uint8_t psn;
 164         bool have_psn = read_physical_slot_number(rp, &psn);
 165
 166         struct device *dev = NULL;
 167         while ((dev = dev_bus_each_child(rp->downstream, dev))) {
 168                 if (!is_pci(dev))
 169                         continue;
 170                 const char *name = acpi_device_name(dev);
 171                 if (!name)
 172                         continue;
 173                 acpigen_write_device(name);
 174                 acpigen_write_ADR_pci_device(dev);
 175                 if (have_psn)
 176                         acpigen_write_name_integer("_SUN", psn);
 177                 acpigen_pop_len();
 178         }
 179 }
 180
 181 void acpigen_write_pci_root_port(const struct device *rp)
 182 {
 183         const char *acpi_scope = acpi_device_scope(rp);
 184         if (!acpi_scope)
 185                 return;
 186         acpigen_write_scope(acpi_scope);
 187
 188         const char *acpi_name = acpi_device_name(rp);
 189         if (!acpi_name)
 190                 return;
 191         acpigen_write_device(acpi_name);
 192         acpigen_write_ADR_pci_device(rp);
 193         acpigen_write_pci_root_port_devices(rp);
 194
 195         acpigen_pop_len();
 196         acpigen_pop_len();
 197 }
 198
 199 void acpigen_write_PRT_pre_routed(const struct device *br)
 200 {
 201         int dev_num = 0;
 202         uint32_t routed_dev_bitmap = 0;
 203         char *entry_count;
 204
 205         if (!is_pci_bridge(br))
 206                 return;
 207
 208         const char *acpi_scope = acpi_device_path(br);
 209         if (!acpi_scope)
 210                 return;
 211
 212         acpigen_write_scope(acpi_scope);
 213         acpigen_write_name("_PRT");
 214         entry_count = acpigen_write_package(0);
 215
 216         struct device *dev = NULL;
 217         while ((dev = dev_bus_each_child(br->downstream, dev))) {
 218                 if (!is_pci(dev))
 219                         continue;
 220                 dev_num = PCI_SLOT(dev->path.pci.devfn);
 221                 if (routed_dev_bitmap & (1 << dev_num))
 222                         continue;
 223
 224                 uint8_t int_line = pci_read_config8(dev, PCI_INTERRUPT_LINE);
 225                 uint8_t int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN);
 226                 if ((int_pin > PCI_INT_MAX) || (int_pin < PCI_INT_A))
 227                         continue;
 228
 229                 acpigen_write_PRT_GSI_entry(dev_num, int_pin - PCI_INT_A, int_line);
 230
 231                 (*entry_count)++;
 232                 routed_dev_bitmap |= (1 << dev_num);
 233         }
 234
 235         acpigen_pop_len();
 236         acpigen_pop_len();
 237 }